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arch: unify stm32 hardware definition names #19114

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2e8b3e8
!arch/stm32f7: unify non-standard hardware definition prefixes
raiden00pl Jun 9, 2026
6457c16
!arch/stm32h5: unify non-standard hardware definition prefixes
raiden00pl Jun 9, 2026
c5750d8
!arch/stm32h7: unify non-standard hardware definition prefixes
raiden00pl Jun 9, 2026
0dbf8da
!arch/stm32l4: unify non-standard hardware definition prefixes
raiden00pl Jun 9, 2026
3994ecc
!arch/stm32l5: unify non-standard hardware definition prefixes
raiden00pl Jun 9, 2026
312b566
!arch/stm32u5: unify non-standard hardware definition prefixes
raiden00pl Jun 9, 2026
1c56c81
!arch/stm32wb: unify non-standard hardware definition prefixes
raiden00pl Jun 9, 2026
b0416b4
!arch/stm32wl5: unify non-standard hardware definition prefixes
raiden00pl Jun 9, 2026
6a999f3
!arch/stm32n6: unify non-standard hardware definition prefixes
raiden00pl Jun 9, 2026
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142 changes: 71 additions & 71 deletions arch/arm/include/stm32f7/chip.h
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Original file line number Diff line number Diff line change
Expand Up @@ -265,43 +265,43 @@
/* Size SRAM */

#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
# define STM32F7_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */
# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
# define STM32_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
# if defined(CONFIG_ARMV7M_HAVE_DTCM)
# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */
# define STM32_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */
# else
# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
# endif
# if defined(CONFIG_ARMV7M_HAVE_ITCM)
# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
# else
# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
# endif
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
# define STM32_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
# if defined(CONFIG_ARMV7M_HAVE_DTCM)
# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */
# define STM32_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */
# else
# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
# endif
# if defined(CONFIG_ARMV7M_HAVE_ITCM)
# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
# else
# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
# endif
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
# define STM32F7_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */
# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
# define STM32_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
# if defined(CONFIG_ARMV7M_HAVE_DTCM)
# define STM32F7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */
# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */
# else
# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
# endif
# if defined(CONFIG_ARMV7M_HAVE_ITCM)
# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
# else
# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
# endif
#else
# error STM32 F7 chip Family not identified
Expand All @@ -310,33 +310,33 @@
/* Common to all Advanced (vs Foundation) Family members */

#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
# define STM32F7_NSPDIFRX 0 /* Not supported */
# define STM32F7_NGPIO 9 /* 9 GPIO ports, GPIOA-I */
# define STM32F7_NI2C 3 /* I2C1-3 */
# define STM32_NSPDIFRX 0 /* Not supported */
# define STM32_NGPIO 9 /* 9 GPIO ports, GPIOA-I */
# define STM32_NI2C 3 /* I2C1-3 */
#else
# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */
# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */
# define STM32F7_NI2C 4 /* I2C1-4 */
# define STM32_NSPDIFRX 4 /* 4 SPDIFRX inputs */
# define STM32_NGPIO 11 /* 11 GPIO ports, GPIOA-K */
# define STM32_NI2C 4 /* I2C1-4 */
#endif

/* Common to all Family members */

# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
# define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */
# define STM32F7_NUSART 4 /* USART1-3 and 6 */
# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */
# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */
# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */
# define STM32F7_NSAI 2 /* SAI1-2 */
# define STM32F7_NDMA 2 /* DMA1-2 */
# define STM32F7_NADC 3 /* 12-bit ADC1-3, number of channels vary */
# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */
# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32F7_NCRC 1 /* CRC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32_NUART 4 /* UART 4-5 and 7-8 */
# define STM32_NUSART 4 /* USART1-3 and 6 */
# define STM32_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */
# define STM32_NUSBOTGFS 1 /* USB OTG FS */
# define STM32_NUSBOTGHS 1 /* USB OTG HS */
# define STM32_NSAI 2 /* SAI1-2 */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NADC 3 /* 12-bit ADC1-3, number of channels vary */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */

/* TBD FPU Configuration */

Expand All @@ -351,82 +351,82 @@
/* Diversification based on Family and package */

#if defined(CONFIG_STM32F7_HAVE_FMC)
# define STM32F7_NFMC 1 /* Have FMC memory controller */
# define STM32_NFMC 1 /* Have FMC memory controller */
#else
# define STM32F7_NFMC 0 /* No FMC memory controller */
# define STM32_NFMC 0 /* No FMC memory controller */
#endif
#if defined(CONFIG_STM32F7_HAVE_ETHRNET)
# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
#else
# define STM32F7_NETHERNET 0 /* No 100/100 Ethernet MAC */
# define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */
#endif
#if defined(CONFIG_STM32F7_HAVE_RNG)
# define STM32F7_NRNG 1 /* Random number generator (RNG) */
# define STM32_NRNG 1 /* Random number generator (RNG) */
#else
# define STM32F7_NRNG 0 /* No Random number generator (RNG) */
# define STM32_NRNG 0 /* No Random number generator (RNG) */
#endif

#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6)
# define STM32F7_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */
# define STM32_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */
#elif defined(CONFIG_STM32F7_HAVE_SPI5)
# define STM32F7_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */
# define STM32_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */
#elif defined(CONFIG_STM32F7_HAVE_SPI4)
# define STM32F7_NSPI 4 /* SPI1-4 V series */
# define STM32_NSPI 4 /* SPI1-4 V series */
#else
# define STM32F7_NSPI 3 /* SPI1-3 R series */
# define STM32_NSPI 3 /* SPI1-3 R series */
#endif

#if defined(CONFIG_STM32F7_HAVE_SDMMC2)
# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */
# define STM32_NSDMMC 2 /* 2 SDMMC interfaces */
#else
# define STM32F7_NSDMMC 1 /* 1 SDMMC interface */
# define STM32_NSDMMC 1 /* 1 SDMMC interface */
#endif
#if defined(CONFIG_STM32F7_HAVE_CAN3)
# define STM32F7_NCAN 3 /* CAN1-3 */
# define STM32_NCAN 3 /* CAN1-3 */
#elif defined(CONFIG_STM32F7_HAVE_CAN2)
# define STM32F7_NCAN 2 /* CAN1-2 */
# define STM32_NCAN 2 /* CAN1-2 */
#else
# define STM32F7_NCAN 1 /* CAN1 only */
# define STM32_NCAN 1 /* CAN1 only */
#endif
#if defined(CONFIG_STM32F7_HAVE_DCMI)
# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#else
# define STM32F7_NDCMI 0 /* No Digital camera interface (DCMI) */
# define STM32_NDCMI 0 /* No Digital camera interface (DCMI) */
#endif
#if defined(CONFIG_STM32F7_HAVE_DSIHOST)
# define STM32F7_NDSIHOST 1 /* Have MIPI DSI Host */
# define STM32_NDSIHOST 1 /* Have MIPI DSI Host */
#else
# define STM32F7_NDSIHOST 0 /* No MIPI DSI Host */
# define STM32_NDSIHOST 0 /* No MIPI DSI Host */
#endif
#if defined (CONFIG_STM32F7_HAVE_LTDC)
# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
# define STM32_NLCDTFT 1 /* One LCD-TFT */
#else
# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
# define STM32_NLCDTFT 0 /* No LCD-TFT */
#endif
#if defined(CONFIG_STM32F7_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */
# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
# define STM32_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
#else
# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */
# define STM32_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */
#endif
#if defined(CONFIG_STM32F7_HAVE_JPEG)
#define STM32F7_NJPEG 1 /* One JPEG Converter */
#define STM32_NJPEG 1 /* One JPEG Converter */
#else
#define STM32F7_NJPEG 0 /* No JPEG Converter */
#define STM32_NJPEG 0 /* No JPEG Converter */
#endif
#if defined(CONFIG_STM32F7_HAVE_CRYP)
#define STM32F7_NCRYP 1 /* One CRYP engine */
#define STM32_NCRYP 1 /* One CRYP engine */
#else
#define STM32F7_NCRYP 0 /* No CRYP engine */
#define STM32_NCRYP 0 /* No CRYP engine */
#endif
#if defined(CONFIG_STM32F7_HAVE_HASH)
#define STM32F7_NHASH 1 /* One HASH engine */
#define STM32_NHASH 1 /* One HASH engine */
#else
#define STM32F7_NHASH 0 /* No HASH engine */
#define STM32_NHASH 0 /* No HASH engine */
#endif
#if defined(CONFIG_STM32F7_HAVE_DFSDM)
#define STM32F7_NDFSDM 4 /* One set of 4 Digital filters */
#define STM32_NDFSDM 4 /* One set of 4 Digital filters */
#else
#define STM32F7_NDFSDM 0 /* No Digital filters */
#define STM32_NDFSDM 0 /* No Digital filters */
#endif

/* NVIC priority levels *****************************************************/
Expand Down
82 changes: 41 additions & 41 deletions arch/arm/include/stm32h5/chip.h
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Original file line number Diff line number Diff line change
Expand Up @@ -34,65 +34,65 @@
****************************************************************************/

#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32H5_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32H5_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */
# define STM32H5_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */
# define STM32_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */
# define STM32_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */
#elif defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32H5_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32H5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
# define STM32H5_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */
# define STM32_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
# define STM32_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */
#else
# error "Unsupported STM32H5 chip"
#endif

#define STM32H5_NFSMC (1) /* Have FSMC memory controller */
#define STM32H5_NATIM (2) /* Two advanced timers TIM1 and TIM8 */
#define STM32H5_NGTIM32 (2) /* 32-bit general timers TIM2 and 5 with DMA */
#define STM32H5_NGTIM16 (2) /* 16-bit general timers TIM3 and 4 with DMA */
#define STM32H5_NGTIMNDMA (3) /* 16-bit general timers TIM15-17 without DMA */
#define STM32H5_NBTIM (2) /* Two basic timers, TIM6-7 */
#define STM32H5_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */
#define STM32H5_NRNG (1) /* Random number generator (RNG) */
#define STM32_NFSMC (1) /* Have FSMC memory controller */
#define STM32_NATIM (2) /* Two advanced timers TIM1 and TIM8 */
#define STM32_NGTIM32 (2) /* 32-bit general timers TIM2 and 5 with DMA */
#define STM32_NGTIM16 (2) /* 16-bit general timers TIM3 and 4 with DMA */
#define STM32_NGTIMNDMA (3) /* 16-bit general timers TIM15-17 without DMA */
#define STM32_NBTIM (2) /* Two basic timers, TIM6-7 */
#define STM32_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */
#define STM32_NRNG (1) /* Random number generator (RNG) */

#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32H5_NUART (6) /* UART 4-5, 7-8, 9, 12 */
# define STM32H5_NUSART (5) /* USART 1-3, 6, 10-11 */
# define STM32_NUART (6) /* UART 4-5, 7-8, 9, 12 */
# define STM32_NUSART (5) /* USART 1-3, 6, 10-11 */
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32H5_NUART (2) /* UART 4-5 */
# define STM32H5_NUSART (4) /* USART 1-3, 6*/
# define STM32_NUART (2) /* UART 4-5 */
# define STM32_NUSART (4) /* USART 1-3, 6*/
#endif

#define STM32H5_NLPUART (1) /* LPUART 1 */
#define STM32H5_QSPI (0) /* No QuadSPI1 */
#define STM32H5_OCTOSPI (1) /* OCTOSPI1*/
#define STM32_NLPUART (1) /* LPUART 1 */
#define STM32_QSPI (0) /* No QuadSPI1 */
#define STM32_OCTOSPI (1) /* OCTOSPI1*/

#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32H5_NSPI (6) /* SPI1-SPI6 */
# define STM32H5_NI2C (4) /* I2C1-4 */
# define STM32_NSPI (6) /* SPI1-SPI6 */
# define STM32_NI2C (4) /* I2C1-4 */
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32H5_NSPI (3) /* SPI1-SPI3 */
# define STM32H5_NI2C (3) /* I2C1-3 */
# define STM32_NSPI (3) /* SPI1-SPI3 */
# define STM32_NI2C (3) /* I2C1-3 */
#endif

#define STM32H5_NSWPMI (0) /* No SWPMI1 */
#define STM32H5_NUSBOTGFS (0) /* USB OTG FS */
#define STM32H5_NUSBFS (1) /* No USB FS */
#define STM32H5_NCAN (2) /* CAN1 */
#define STM32H5_NSAI (2) /* SAI1-2 */
#define STM32_NSWPMI (0) /* No SWPMI1 */
#define STM32_NUSBOTGFS (0) /* USB OTG FS */
#define STM32_NUSBFS (1) /* No USB FS */
#define STM32_NCAN (2) /* CAN1 */
#define STM32_NSAI (2) /* SAI1-2 */

#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32H5_NSDMMC (2) /* SDMMC interface */
# define STM32_NSDMMC (2) /* SDMMC interface */
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32H5_NSDMMC (1) /* SDMMC interface */
# define STM32_NSDMMC (1) /* SDMMC interface */
#endif

#define STM32H5_NDMA (2) /* DMA1-2 */
#define STM32H5_NPORTS (8) /* 8 GPIO ports, GPIOA-GPIOI */
#define STM32H5_NADC (2) /* 12-bit ADC1, up to 20 channels */
#define STM32H5_NDAC (1) /* 12-bit DAC1 */
#define STM32H5_NCRC (1) /* CRC */
#define STM32H5_NCOMP (0) /* Comparators */
#define STM32H5_NOPAMP (0) /* Operational Amplifiers */
#define STM32_NDMA (2) /* DMA1-2 */
#define STM32_NPORTS (8) /* 8 GPIO ports, GPIOA-GPIOI */
#define STM32_NADC (2) /* 12-bit ADC1, up to 20 channels */
#define STM32_NDAC (1) /* 12-bit DAC1 */
#define STM32_NCRC (1) /* CRC */
#define STM32_NCOMP (0) /* Comparators */
#define STM32_NOPAMP (0) /* Operational Amplifiers */

/* NVIC priority levels *****************************************************/

Expand All @@ -104,9 +104,9 @@
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */

#if defined(CONFIG_STM32H5_HAVE_ETHERNET)
# define STM32H5_NETHERNET 1 /* Ethernet MAC */
# define STM32_NETHERNET 1 /* Ethernet MAC */
#else
# define STM32H5_NETHERNET 0 /* No Ethernet MAC */
# define STM32_NETHERNET 0 /* No Ethernet MAC */
#endif

#endif /* __ARCH_ARM_INCLUDE_STM32H5_CHIP_H */
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