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1. f1-reaction-timer-fpga f1-reaction-timer-fpga Public

   F1 starting light reaction timer on Intel MAX10 FPGA. SystemVerilog FSM, LFSR random delay, hierarchical clock management. Imperial College London (Grade: A).

   SystemVerilog

2. eda-analyser eda-analyser Public

   Python tool to automate Quartus STA and synthesis report parsing. Extracts WNS, TNS, and resource utilisation metrics with visual summaries.

   Python

3. C-First-Year-Projects C-First-Year-Projects Public

   This repository gathers a selection of my first-year C++ programming projects completed as part of the Electrical and Electronic Engineering course at Imperial College London. Each project demonstr…

   C++

4. reborn-hand-unlimbited-arm reborn-hand-unlimbited-arm Public

   Custom upper-limb prosthetic hand designed and 3D-printed for a child with agenesis via e-Nable France. CAD files, assembly notes, and electronics documentation.