More real mode instruction and interrupt mechanics tests.

[superfury]

A few more tests I've added just now:

• SIDT/SGDT instructions.
• LGDT/LIDT instructions (these are done from real mode to prevent faulting during tests).
• XLAT instruction (from real mode).
• Real mode interrupts
• Flag instructions (including the still unused CMC flag instruction)

I've also adjusted the POST codes to add the new tests (included in the 128K ROM only). And updated the Readme to match the new POST codes.

That just leaves the following instructions and mechanics untested:

• Debugger register (DR0-DR7) and their effects.
• ICEBP (alternate INT1. Same as a normal breakpoint, but doesn't set the single step bit in DR6). This also includes single-step traps (real and protected mode), TSS single step flag and falls under the same category as the debugger registers.
• LAR instruction
• LSL instruction
• LMSW instruction (including it's behaviour to keep the protected mode bit set to matter what is loaded).
• LTR instruction (including busy bit already set, causing a fault).
• NOP 'instruction' (not sure this is worth testing though).
• INS/OUTS string instructions

[superfury]

Just thought of a little improvement to the real and protected mode interrupt tests: check if the interrupt flag is cleared (both for real mode interrupts and the PL0 protected mode interrupt). Just need to implement that test.

[superfury]

The latest changes also check if the interupt flag is cleared (both for the real mode interrupts and protected mode interrupt elevating to ring 0) and properly set on the stack (only the case of it being set is checked however, no check for interrupt trap gates is performed).

I did need to move the int 20h interrupt handler to the extension space to make room for the newly changed instructions (the upper 64K ROM ran out of room to compile it). Thus also requiring the privilege change check (from CPL 3 user mode to CPL 0 kernel mode through a non-conforming segment and DPL 3 gate) to require the 128K ROM now (otherwise, it wouldn't fit).

[barotto]

I pass the tests.

However:

1. You put POST 2 between Conditional jumps and Loops of POST 1, should be moved after Loops.
2. NASM gives error "TIMES value -4 is negative" when ROM128 and TEST_UNDEF are both 1.

Also you changed most POST codes, don't forget to update intel-opcodes.ods accordingly.
Alternatively, instead of moving codes down to make space, we can use free codes in the 0x23-0xdf range, despite not being in order. Real BIOS' don't use codes in order anyway, I don't think it's a problem.

[superfury]

The times -4 error means that the 64K ROM area is too small to contain the data (overflowing the FFF0 address by 4 bytes in this case). I've already moved some code down to fix that error I've got earlier. Unless I move even more code down to the lower area to fix that too (requiring the 128K ROM for even more tests).

[superfury]

I've compressed the POST 8/9/A tests a bit, removing some of their needs to jump to and from the upper ROM half. This should give just enough spare room to get those configurations to work properly in all cases from what I can see.

Reverting the POST codes right now is a bit of an issue? It's been moved twice already, so it's kind of difficult to figure out what their originals were? Unless I revert all of them and simply modify the newly added ones?

[superfury]

I've reverted the POST codes back to what they were during the last pull request. Then modified the newly added POST codes to use POST 7 (which was unused, now used for the real mode interrupt test) and 1D-1F for the other newly added tests. That still leaves POST A that was split up into the 20-22 POST codes as a gap in the used POST code range, but that's not that much of an issue, since it's not documented in the intel-opcodes.ods file (it tests mechanics, not instructions)?