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4 changes: 2 additions & 2 deletions p3-pic.md
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ the CPU. These interrupt pins were labelled IRQ0 to IRQ7 for primary, and IRQ8 t
IRQ15 for the secondary. In total, we can effectively get 15 (16 minus primary's
pin 2) interrupt pins.

By a matter of convention, timer is attached on IRQ0, keyboard on IRQ1,
As a matter of convention, timer is attached on IRQ0, keyboard on IRQ1,
real-time clock on IRQ8, mouse on IRQ12, IDE controller on IRQ14, etc. Some of
these IRQs are defined in `traps.h`. However, since there were only 15 pins,
some devices started sharing the pins which created complications in managing
Expand Down Expand Up @@ -47,4 +47,4 @@ In a similar manner, IOAPICs are also memory-mapped, located at `0xFEC00000`.
`ioapic.c` just reads how many interrupt pins are on the IOAPIC in `maxintr`
variable and disables them. They will be later enabled when we are ready to
handle interrupts. You can read more about IOAPICs
[here](https://web.archive.org/web/20161130153145/http://download.intel.com/design/chipsets/datashts/29056601.pdf).
[here](https://web.archive.org/web/20161130153145/http://download.intel.com/design/chipsets/datashts/29056601.pdf).