Fix SIGILL crash on CPUs without AVX-512#6
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GavinPalmer1984 wants to merge 1 commit intocomputerex:mainfrom
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Fix SIGILL crash on CPUs without AVX-512#6GavinPalmer1984 wants to merge 1 commit intocomputerex:mainfrom
GavinPalmer1984 wants to merge 1 commit intocomputerex:mainfrom
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The #pragma GCC target directives in simd_dot.c, simd_qq_dot.c, and cpool.c forced AVX-512 instruction generation regardless of the build machine's capabilities. This overrode the -march=native flag already present in CGo CFLAGS, causing GCC to auto-vectorize with AVX-512 instructions that crash (SIGILL) on CPUs without AVX-512 support. Remove the target pragmas entirely and rely on -march=native, which already detects the CPU at compile time. This means: - AVX-512 machines: GCC auto-vectorizes with AVX-512 as before - AVX2-only machines: GCC correctly limits to AVX2/FMA/F16C - No performance regression on capable hardware Fixes computerex#4 Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Summary
#pragma GCC target(...)inquant/simd_dot.c,quant/simd_qq_dot.c, andquant/cpool.cforced AVX-512 instruction generation regardless of the build machine-march=nativeflag already present in CGo CFLAGS, causing GCC's auto-vectorizer to emit EVEX-prefixed AVX-512 instructionsSIGILLcrash on CPUs without AVX-512 (Intel pre-11th gen, AMD pre-Zen 4)Fix
Remove the
#pragma GCC target(...)directives entirely and rely on-march=native(already in#cgo CFLAGS), which detects CPU capabilities at compile time:The pragmas were originally added to "avoid CGo flag restrictions", but
-march=nativealready handles this correctly.Test plan
-march=nativeenables the same features)Fixes #4
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