baseline arm PR105.0: single-machine dual-GPU (no RPC), PR #110 config reference

[ddvnguyen]

Baseline arm derived from the PR #110 verified config with the topology reduced to a single machine: both GPUs in one llama-server process, RPC peer removed. Binary and all other knobs identical to PR #110 — only the launch topology changes.

Commits

1. docs: PR105.0 arm spec (docs/arms/pr105-single-machine-baseline.md): config-deltas table vs PR feat(server): --parallel-ctx-threshold admission gate + UM prefetch net (hydra#747 baseline) #110, canonical launch line, hypothesis, verification plan with pass criteria, test plan.

Config deltas vs PR #110 rig

Item	PR #110 (RPC)	PR105.0
Topology	CUDA0 (5060 Ti) + rpc-server on CUDA1 (3060)	one process: -dev CUDA0,CUDA1
Split / gate / KV / MTP / UM / build	-sm row -ts 27,38, threshold 100000, -np 2, K q8_0 / V q5_1, --spec-type draft-mtp, UM on, FA-all-quants build	unchanged, same binary

GGML_RPC=ON stays in the build so one binary serves this arm and the upcoming PR103.0 (GDN cache-cpy fusion) / PR104.x (mixed-quant row sharding) arms.

Hypothesis

Prior single-machine trial showed dropping RPC does not materially change decode — the wall is the 3060's bandwidth x VRAM-forced share, not RPC overhead. Expected: within-noise parity with the PR #110 bar. Value of the arm:

1. clean reference topology for PR103.0 / PR104.x (no RPC confound),
2. removes the RPC peer version-skew failure mode,
3. verifies the PR feat(server): --parallel-ctx-threshold admission gate + UM prefetch net (hydra#747 baseline) #110 UM prefetch net behaves identically without RPC.

Verification plan (arm102 bars as reference)

• Single decode: bar 40.1 t/s (kv_unified off, V q5_1) -> pass mean >= 39.0 t/s over >= 5 loops
• n=2 concurrent agg: bar 49.2-52.6 -> within band or better
• Prefill: bar 405 t/s -> >= 400 t/s
• Admission gate: defer + auto-admit on slot release observed once, 0 spurious defers
• Greedy determinism: byte-identical run-to-run, cold/warm
• VRAM: GPU0 <= 15.5 GB, GPU1 <= 11.5 GB (no UM oversubscription)

Primary cell only for first pass; secondary cell (kv_unified on / V q4_1, bar 38.4) once primary passes.

Test plan

• Build: same flags as PR feat(server): --parallel-ctx-threshold admission gate + UM prefetch net (hydra#747 baseline) #110, GGML_CUDA_FORCE_CUBLAS off
• Boot: /health 200, both devices in device log
• Gate defer/auto-admit observed once, 0 spurious defers
• Single decode >= 5 loops vs bar
• n=2 concurrent agg
• Greedy determinism check
• Results recorded; PR103.0/PR104.x rebase on this topology

AI usage disclosure: YES — arm spec and PR body drafted by AI (opencode) from the PR #110 verified config and local flag verification (common/arg.cpp, docs/speculative.md); -c 296000 (per-slot 148000 x 2) is carried from the arm102 record and flagged in the doc for confirmation against the arm102 yml before first boot. Repo owner to verify launch line on the rig before running.

[ddvnguyen]

Amended the launch spec (leader review finding): added the flags the 747.0 reference yml sets that were missing from the literal command — --rope-scaling yarn --rope-scale 5 --yarn-orig-ctx 32768, draft KV types -ctkd q8_0 -ctvd q5_1, and --cache-prompt --cache-reuse 64 --cache-idle-slots --cache-ram 16384. Also corrected the -c 296000 citation: the bar source is 747.0-baseline-nokvu-p2-vq51-th100k.yml (not the arm102 yml, which is parallel=3 / ctx=438528 / V q4_1 and sources the secondary-cell bar). Flags verified against common/arg.cpp on baseline. Docs-only; no config semantics changed beyond making the spec actually reproduce the reference bars.