Verilog: fix unsigned/signed parameter without explicit range#1902
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Verilog: fix unsigned/signed parameter without explicit range#1902kroening wants to merge 1 commit into
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When a parameter is declared with only a signing keyword and no explicit range (e.g., parameter unsigned P = 8'shff), the width should be derived from the value and only the signedness adjusted. Previously, this was incorrectly elaborated as a 1-bit type.
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When a parameter is declared with only a signing keyword and no explicit range (e.g.,
parameter unsigned P = 8'shff), the width should be derived from the value and only the signedness adjusted.Previously, this was incorrectly elaborated as a 1-bit type, because
elaborate_type(ID_unsigned)with nil subtype defaults tounsignedbv_typet{1}.Changes:
src/verilog/verilog_elaborate.cpp: Handle unsigned/signed with nil subtype inelaborate_symbol_recby deriving width from the value, then applying the signedness.regression/verilog/parameters/unsigned_parameter1.desc: Changed from KNOWNBUG to CORE.