Verilog: SystemVerilog interfaces#1907
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Per IEEE 1800-2017 section 25, implement basic SystemVerilog interface support: - Parser: interface declarations (A.1.5), modport declarations (A.2.9), interface port declarations (A.2.1.2) - Elaboration: register interfaces in symbol table - Type checking: interface instances as module instances, hierarchical access to interface members - Synthesis: hierarchical identifier on LHS of assignments Interface port binding (passing interface instances to module ports) is not yet implemented and remains as KNOWNBUG.
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Adds support for SystemVerilog interfaces (IEEE 1800-2017 A.2.9):