feat(pvh): implement aarch64 PVH checks - #162
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| /// rdmsr 0xC0010114 # bit 4 = SVMDIS; must be 0 | ||
| /// ``` | ||
| async fn check_virtualization(&self) -> CheckResult { | ||
| async fn check_virtualization_x86(&self) -> CheckResult { |
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| async fn check_virtualization_x86(&self) -> CheckResult { | |
| async fn check_virtualization(&self) -> CheckResult { |
Let's keep this as arch-agnostic, have two versions of this function with the same signature, and use target_arch based conditional compilation so that only one or the other gets built based on the current arch.
All x86_64 specific stuff should be conditionally compiled with a target_arch = x86_64 gate, and all arm64 stuff should be target_arch = aarch64 gated
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@bleggett done, let me know if the current state is acceptable
The arm spec defines a model specific register called ID_AA64PFR0_EL1 which exposes CPU features, hardware assisted virtualization support is encoded in bits [11:8] of that register. Implemet PVH checks through reading this register's value. Allow unused in pvh.rs because the actual compiled code will vary based on the architecture and may leave alot of types, imports and functions unused. Signed-off-by: aerosouund <aerosound161@gmail.com>
| #[cfg(target_arch = "aarch64")] | ||
| async fn check_virtualization(&self) -> CheckResult { | ||
| // On aarch64, the cpu features are available through a model specific | ||
| // register called ID_AA64PFR0_EL1. This register can be read normally from |
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Looking more closely at this - I'm not actually sure this will work on real hardware?
The kernel docs specifically say that EL2 is not visible/would be zeroed if inspected from userspace.
Without testing this on a real arm64 (where, if I read the kernel docs correctly, it will always return 0 and fail) I don't think we can say this will work.
I'm not sure what would work here, other than a kmod, which is too heavyweight for sure.
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Oh actually - I think we don't need/want this either way - Xen only supports one kind of backend on arm64 anyway, so there's no PV vs PVH capability we need to check for.
Which means we don't need this - I've closed #156 as Not Planned. Thanks, and sorry - I should have looked at this sooner!
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@bleggett
no worries at all. thanks for the info. i certainly learned a thing or two working on this!
closing
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Explanation
The arm spec defines a model specific register called
ID_AA64PFR0_EL1which exposes CPU features, hardware assisted virtualization support is encoded in bits [11:8] of that register. Implemet PVH checks through reading this register's value.Allow unused in pvh.rs because the actual compiled code will vary based on the architecture and may leave alot of types, imports and functions unused.
Fixes: #156
Example failed run:
Note: I don't currently have access to a bare metal arm host with hardware virtualization so i cannot verify the success scenario. I will see how i can get around this
cc: @antoineco @bleggett