feat(dlc10): pure-Rust driver for Xilinx Platform Cable USB II + SPI flash#593

Merged

gHashTag merged 22 commits into

feat/trios-bridgefrom

feat/dlc10-rust

May 14, 2026

Commits on May 14, 2026

feat(dlc10): pure-Rust driver + SPI flash programming

claude
authored and
Perplexity Computer
committed
fix(dlc10): use real 22956-byte Cypress FX2 firmware (was placeholder)

Trinity Dev
authored and
Perplexity Computer
committed
feat(dlc10): debug subcommand + verbose sram for DONE=LOW diagnosis

claude
authored and
Perplexity Computer
committed
fix(dlc10): RTI parking in Type-1 read + INIT_B poll after JPROGRAM

claude
authored and
Perplexity Computer
committed
fix(dlc10): mirror openFPGALoader dumpRegister — per-word Update-DR

claude
authored and
Perplexity Computer
committed
refactor(tri): centralize FPGA + hooks in Rust, remove Python/shell legacy

claude
authored and
Perplexity Computer
committed
fix(fpga): SPI flash JEDEC=FF FF FF on QMTech XC7A100T — bit-reverse + capture skew

claude
authored and
Perplexity Computer
committed
feat(fpga): openXC7 build path for QMTech-specific proxy bitstream

claude
authored and
Perplexity Computer
committed
fix(tri): nextpnr-himbaechel xilinx uses -o xdc=/-o fasm= not --xdc/--fasm

gHashTag
authored and
Perplexity Computer
committed
feat(fpga): openXC7 chipdb setup helper for nextpnr-himbaechel

Claude Agent
authored and
Perplexity Computer
committed
feat(fpga): docker vivado build path for QMTech proxy

claude
authored and
Perplexity Computer
committed
fix(fpga): correct himbaechel device name to xc7a100tfgg676-1

authored and
Perplexity Computer
committed
docs(fpga): openXC7 native FGG676 status — chipdb OK, config-pin routing blocked

claude
authored and
Perplexity Computer
committed
fix(dlc10): SPI capture uses Migen JTAG2SPI framing (marker + BE length + MSB-first)

claude
authored and
Perplexity Computer
committed
feat(fpga): docker vivado 2025.2 image prep for FGG676 proxy

claude
authored and
Perplexity Computer
committed
docs(fpga): docker-vivado FGG676 status — image build in progress

claude
authored and
Perplexity Computer
committed
feat(fpga): deploy CI-built spiOverJtag_xc7a100tfgg676.bit proxy bitstream

claude
authored and
Perplexity Computer
committed
feat(dlc10): fix bring-up, read_cfg_reg, and STARTUPCLK — DONE=HIGH achieved

claude
authored and
Perplexity Computer
committed
feat(dlc10): port spi_put_v2 — JEDEC 20 BA 17 reads end-to-end

claude
authored and
Perplexity Computer
committed
feat(dlc10): SPI flash write/verify works end-to-end — 3-month blocker fully resolved

claude
authored and
Perplexity Computer
committed
feat(dlc10): default per-byte bitswap of bitstream payload for Master SPI boot

claude
authored and
Perplexity Computer
committed
fix(ci): L1 traceability accepts Refs/Updates/Resolves as valid issue links (#605)

gHashTag
authored and
Perplexity Computer
committed

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feat(dlc10): pure-Rust driver for Xilinx Platform Cable USB II + SPI flash#593

feat(dlc10): pure-Rust driver for Xilinx Platform Cable USB II + SPI flash#593
gHashTag merged 22 commits into
feat/trios-bridgefrom
feat/dlc10-rust

Commits on May 14, 2026

feat(dlc10): pure-Rust driver + SPI flash programming

fix(dlc10): use real 22956-byte Cypress FX2 firmware (was placeholder)

feat(dlc10): debug subcommand + verbose sram for DONE=LOW diagnosis

fix(dlc10): RTI parking in Type-1 read + INIT_B poll after JPROGRAM

fix(dlc10): mirror openFPGALoader dumpRegister — per-word Update-DR

refactor(tri): centralize FPGA + hooks in Rust, remove Python/shell legacy

fix(fpga): SPI flash JEDEC=FF FF FF on QMTech XC7A100T — bit-reverse + capture skew

feat(fpga): openXC7 build path for QMTech-specific proxy bitstream

fix(tri): nextpnr-himbaechel xilinx uses -o xdc=/-o fasm= not --xdc/--fasm

feat(fpga): openXC7 chipdb setup helper for nextpnr-himbaechel

feat(fpga): docker vivado build path for QMTech proxy

fix(fpga): correct himbaechel device name to xc7a100tfgg676-1

docs(fpga): openXC7 native FGG676 status — chipdb OK, config-pin routing blocked

fix(dlc10): SPI capture uses Migen JTAG2SPI framing (marker + BE length + MSB-first)

feat(fpga): docker vivado 2025.2 image prep for FGG676 proxy

docs(fpga): docker-vivado FGG676 status — image build in progress

feat(fpga): deploy CI-built spiOverJtag_xc7a100tfgg676.bit proxy bitstream

feat(dlc10): fix bring-up, read_cfg_reg, and STARTUPCLK — DONE=HIGH achieved

feat(dlc10): port spi_put_v2 — JEDEC 20 BA 17 reads end-to-end

feat(dlc10): SPI flash write/verify works end-to-end — 3-month blocker fully resolved

feat(dlc10): default per-byte bitswap of bitstream payload for Master SPI boot

fix(ci): L1 traceability accepts Refs/Updates/Resolves as valid issue links (#605)