fix(codegen): R-SI-1 (no mul) + R-NAME (field underscore) in VerilogCodegen#699
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fix(codegen): R-SI-1 (no mul) + R-NAME (field underscore) in VerilogCodegen#699gHashTag wants to merge 2 commits into
gHashTag wants to merge 2 commits into
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Commits on May 18, 2026
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