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- 🌱 Currently learning VLSI Physical Design Flow (PNR)
- 🔧 Hands-on with Floorplanning, Placement, CTS, Routing, STA
- 🧠 Strong understanding of Setup/Hold Timing, Clock Skew, Slack, Constraints
- 🛠️ Experience with Cadence Innovus & Tempus
- 📐 Interested in Low Power Design, Timing Closure & Backend Optimization
- 👯 Looking to collaborate on VLSI / EDA automation & scripting projects
- 👨💻 Projects available at:
👉 https://github.com/gauravx1102 - 💬 Ask me about STA, Physical Design Flow, Timing Reports, SDC
- 📫 Reach me at fularagaurav1102@gmail.com
- Physical Design Flow:
Floorplanning → Placement → CTS → Routing → Signoff - Static Timing Analysis (STA)
Setup/Hold, Skew, Uncertainty, OCV, Path Analysis - Constraints:
SDC (Clocks, IO Delays, False/Multicycle Paths) - Reports Analysis:
Timing, Power, Area, QoR - Tools:
Cadence Innovus, Cadence Tempus - Scripting:
Perl, Tcl, basic Shell (for flow automation)