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Add RISC-V target detection#75

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carlosqwqqwq wants to merge 1 commit into
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carlosqwqqwq:riscv-crc32c
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Add RISC-V target detection#75
carlosqwqqwq wants to merge 1 commit into
google:mainfrom
carlosqwqqwq:riscv-crc32c

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@carlosqwqqwq

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Why

crc32c did not expose a dedicated RISC-V target in its CMake architecture selection, so riscv configurations could still flow through x86 or ARM feature probes indirectly. This patch makes the baseline RISC-V path explicit while keeping the portable implementation path.

What changed

  • Detect the effective target architecture in CMake using CMAKE_SYSTEM_PROCESSOR, CMAKE_HOST_SYSTEM_PROCESSOR, and CMAKE_CXX_COMPILER_TARGET.
  • Generate CRC32C_TARGET_RISCV for RISC-V configurations.
  • Only probe _mm_prefetch and SSE4.2 intrinsics for x86 targets.
  • Only probe ARM CRC32/PMULL and getauxval support for ARM64 targets.
  • Keep RISC-V configurations on the existing portable implementation path without injecting x86 or ARM compile flags.

Verification

  • Ran native CMake configuration with Ninja, MinGW GCC, tests enabled, benchmarks disabled, glog disabled, and install disabled.
  • Built the native project successfully with cmake --build build-codex-native --parallel 4.
  • Ran ctest --test-dir build-codex-native --output-on-failure; crc32c_tests and crc32c_capi_tests both passed.
  • Checked generated native crc32c_config.h: HAVE_MM_PREFETCH=1, HAVE_SSE42=1, and CRC32C_TARGET_RISCV=0.
  • Ran simulated riscv64 CMake configuration with CMAKE_SYSTEM_NAME=Linux, CMAKE_SYSTEM_PROCESSOR=riscv64, and CMAKE_TRY_COMPILE_TARGET_TYPE=STATIC_LIBRARY.
  • Built the simulated riscv64 static library successfully with cmake --build build-codex-riscv --target crc32c --parallel 4.
  • Checked generated RISC-V crc32c_config.h: CRC32C_TARGET_RISCV=1, HAVE_MM_PREFETCH=0, HAVE_SSE42=0, HAVE_ARM64_CRC32C=0, HAVE_STRONG_GETAUXVAL=0, and HAVE_WEAK_GETAUXVAL=0.
  • Checked build-codex-riscv/compile_commands.json: no -msse4.2, /arch:AVX, or -march=armv8-a+crc+crypto flags were present.

Notes

This is a conservative portability patch. It does not add RISC-V hardware CRC instructions or RVV acceleration. No real riscv64 cross-toolchain or hardware validation was available on the local Windows host.

@google-cla

google-cla Bot commented Jun 11, 2026

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Thanks for your pull request! It looks like this may be your first contribution to a Google open source project. Before we can look at your pull request, you'll need to sign a Contributor License Agreement (CLA).

View this failed invocation of the CLA check for more information.

For the most up to date status, view the checks section at the bottom of the pull request.

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