feat: FPGA VANC timecode inserter for Ninja V recording trigger by alfskaar · Pull Request #605 · hd-zero/hdzero-goggle

alfskaar · 2026-04-14T20:00:36Z

Summary

Sample Verilog module and documentation for injecting SMPTE 12M-2 timecode as VANC (Vertical Ancillary Data) packets into the HDMI video blanking interval.

Background

The Atomos Ninja V "HDMI Device" trigger modes (Canon EOS R, Sony ILCE-7SM3, etc.) use VANC timecode — not HDMI InfoFrames — to detect recording state.

HDfury captures of a real Canon EOS R confirmed all InfoFrames are byte-for-byte identical between REC ON and REC OFF. The trigger mechanism is SMPTE 12M-2 timecode embedded at the pixel level during vertical blanking.

The IT66121 HDMI transmitter cannot inject VANC — it only handles InfoFrames and audio. VANC must be injected by the FPGA before the video reaches the IT66121.

Files

fpga_vanc_timecode/vanc_timecode_inserter.v — Verilog module: line/pixel counters, SMPTE ST 291M packet builder with BCD timecode, insertion state machine, video passthrough mux
fpga_vanc_timecode/README.md — VANC packet format spec, integration notes, blanking line selection, and CPU register interface

Integration

The VANC inserter goes in the FPGA video pipeline:

Camera RX → Frame Buffer → Scaler → [VANC Inserter] → IT66121 Parallel Input

CPU (ARM / Allwinner V536) controls timecode via FPGA registers:

TC_HOURS, TC_MINUTES, TC_SECONDS, TC_FRAMES, TC_ENABLE
ARM increments timecode once per second; FPGA inserts VANC packets every frame

Status

This is sample/reference code for FPGA integration. Software-side Canon EOS R VSIF trigger code exists separately in the firmware (not included in this PR).

Copilot

Pull request overview

Adds reference FPGA logic and documentation to inject SMPTE 12M-2 timecode as a VANC (ST 291M ANC) packet during vertical blanking, intended to trigger Atomos Ninja V recording via VANC timecode presence.

Changes:

Introduces a vanc_timecode_inserter Verilog module with counters, packet builder, and insertion mux.
Adds a README describing the VANC packet structure, integration placement, and CPU register control flow.

Reviewed changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated 8 comments.

File	Description
fpga_vanc_timecode/vanc_timecode_inserter.v	New sample Verilog module for VANC timecode packet generation and insertion into blanking.
fpga_vanc_timecode/README.md	Documentation for packet format and integration guidance for the inserter module.

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Copilot · 2026-04-14T20:05:09Z

+    // Checksum: 9-bit sum of DID through last UDW, then keep [7:0]
+    // (not bit-inverted — SMPTE 291M uses simple sum)
+    checksum = {1'b0, pkt_rom[3]}  + {1'b0, pkt_rom[4]}  + {1'b0, pkt_rom[5]}
+             + {1'b0, pkt_rom[6]}  + {1'b0, pkt_rom[7]}  + {1'b0, pkt_rom[8]}
+             + {1'b0, pkt_rom[9]}  + {1'b0, pkt_rom[10]} + {1'b0, pkt_rom[11]}
+             + {1'b0, pkt_rom[12]} + {1'b0, pkt_rom[13]} + {1'b0, pkt_rom[14]}
+             + {1'b0, pkt_rom[15]} + {1'b0, pkt_rom[16]} + {1'b0, pkt_rom[17]}
+             + {1'b0, pkt_rom[18]} + {1'b0, pkt_rom[19]} + {1'b0, pkt_rom[20]}
+             + {1'b0, pkt_rom[21]};
+    pkt_rom[22] = checksum[7:0];


Checksum handling is internally inconsistent: the header/README describe a 9-bit checksum, but the implementation truncates to checksum[7:0] and stores only 8 bits in pkt_rom[22]. Please align the implementation and documentation on the checksum width/format (and update packet word width accordingly if a 9-bit checksum is intended).