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7 changes: 7 additions & 0 deletions Cargo.lock

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1 change: 1 addition & 0 deletions Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -348,6 +348,7 @@ thiserror = { version = "2", default-features = false }
time = { version = "0.3", default-features = false }
volatile = "0.6"
uhyve-interface = { version = "0.2", optional = true }
seahash = "4.1.0"

[dependencies.smoltcp]
version = "0.13"
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5 changes: 1 addition & 4 deletions src/arch/x86_64/kernel/apic.rs
Original file line number Diff line number Diff line change
Expand Up @@ -886,10 +886,7 @@ pub fn ipi_tlb_flush() {
#[allow(unused_variables)]
pub fn wakeup_core(core_id_to_wakeup: CoreId) {
#[cfg(all(feature = "smp", not(feature = "idle-poll")))]
if core_id_to_wakeup != core_id()
&& !processor::supports_mwait()
&& scheduler::take_core_hlt_state(core_id_to_wakeup)
{
if core_id_to_wakeup != core_id() && !processor::supports_mwait() {
without_interrupts(|| {
let apic_ids = CPU_LOCAL_APIC_IDS.lock();
let local_apic_id = apic_ids[core_id_to_wakeup as usize];
Expand Down
6 changes: 0 additions & 6 deletions src/arch/x86_64/kernel/core_local.rs
Original file line number Diff line number Diff line change
@@ -1,8 +1,6 @@
use alloc::boxed::Box;
use core::arch::asm;
use core::cell::Cell;
#[cfg(feature = "smp")]
use core::sync::atomic::AtomicBool;
use core::sync::atomic::Ordering;
use core::{mem, ptr};

Expand Down Expand Up @@ -34,8 +32,6 @@ pub(crate) struct CoreLocal {
irq_statistics: &'static IrqStatistics,
/// The core-local async executor.
ex: StaticLocalExecutor<RawSpinMutex, RawRwSpinLock>,
#[cfg(feature = "smp")]
pub hlt: AtomicBool,
/// Queues to handle incoming requests from the other cores
#[cfg(feature = "smp")]
pub scheduler_input: InterruptTicketMutex<SchedulerInput>,
Expand Down Expand Up @@ -63,8 +59,6 @@ impl CoreLocal {
irq_statistics,
ex: StaticLocalExecutor::new(),
#[cfg(feature = "smp")]
hlt: AtomicBool::new(false),
#[cfg(feature = "smp")]
scheduler_input: InterruptTicketMutex::new(SchedulerInput::new()),
};
let this = if core_id == 0 {
Expand Down
2 changes: 0 additions & 2 deletions src/arch/x86_64/kernel/interrupts.rs
Original file line number Diff line number Diff line change
Expand Up @@ -82,8 +82,6 @@ pub(crate) fn enable_and_wait() {
);
}
} else {
#[cfg(feature = "smp")]
crate::CoreLocal::get().hlt.store(true, Ordering::Relaxed);
enable_and_hlt();
}
}
Expand Down
14 changes: 0 additions & 14 deletions src/scheduler/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -8,8 +8,6 @@ use alloc::sync::Arc;
use alloc::vec::Vec;
use core::cell::RefCell;
use core::ptr;
#[cfg(all(target_arch = "x86_64", feature = "smp"))]
use core::sync::atomic::AtomicBool;
use core::sync::atomic::{AtomicI32, AtomicU32, Ordering};

use ahash::RandomState;
Expand Down Expand Up @@ -40,8 +38,6 @@ static NO_TASKS: AtomicU32 = AtomicU32::new(0);
#[cfg(feature = "smp")]
static SCHEDULER_INPUTS: SpinMutex<Vec<&InterruptTicketMutex<SchedulerInput>>> =
SpinMutex::new(Vec::new());
#[cfg(all(target_arch = "x86_64", feature = "smp"))]
static CORE_HLT_STATE: SpinMutex<Vec<&AtomicBool>> = SpinMutex::new(Vec::new());
/// Map between Task ID and Queue of waiting tasks
static WAITING_TASKS: InterruptTicketMutex<BTreeMap<TaskId, VecDeque<TaskHandle>>> =
InterruptTicketMutex::new(BTreeMap::new());
Expand Down Expand Up @@ -891,19 +887,9 @@ pub(crate) fn add_current_core() {
core_id.try_into().unwrap(),
&CoreLocal::get().scheduler_input,
);
#[cfg(target_arch = "x86_64")]
CORE_HLT_STATE
.lock()
.insert(core_id.try_into().unwrap(), &CoreLocal::get().hlt);
}
}

#[inline]
#[cfg(all(target_arch = "x86_64", feature = "smp", not(feature = "idle-poll")))]
pub(crate) fn take_core_hlt_state(core_id: CoreId) -> bool {
CORE_HLT_STATE.lock()[usize::try_from(core_id).unwrap()].swap(false, Ordering::Acquire)
}

#[inline]
#[cfg(feature = "smp")]
fn get_scheduler_input(core_id: CoreId) -> &'static InterruptTicketMutex<SchedulerInput> {
Expand Down
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