[LeslieWylie]

MiniMax-H3 converts the decoded clip to FP32 before restoring pixel values. For long clips, those full-clip temporaries can exhaust device memory after decoding has succeeded.

Process the same pixels in 16-frame batches through the existing VideoProcessor. NumPy and PIL results are collected on the CPU; tensor output uses a preallocated result on the original device. Output types, frame order and pixel arithmetic are preserved. Fixes #15119; maintainer feedback on the scope is still pending.

CUDA validation on October 27 compared complete source trees at head 6280cd9a and base b800f828, with normal package imports in separate processes: one NVIDIA L20 (SM89), PyTorch 2.13.0+cu130, CUDA 13.0. The real tiny H3 VAE, modular decode step and VideoProcessor produced bit-identical complete outputs for FP16/BF16/FP32, pt/np/PIL, and both normalization settings. Batch 2 with seven latent frames produced 22 output frames, exercising the 16-frame batch and six-frame tail. Tensor results remained contiguous CUDA tensors.

A separate postprocessing-only check used the same fixed FP16 decoded tensor (2, 3, 97, 128, 128), seed 15070, with the normally imported production step and real processor. A fixture returned that tensor from vae.decode; the VAE was not measured. After one warmup, synchronization and a peak-stat reset, total CUDA peak allocation fell from 90.94 MiB to 30.19 MiB for np/PIL and 72.57 MiB for pt. Incremental peaks above the common live input allocation were 72.75 → 12.00 MiB and 72.75 → 54.38 MiB respectively. All measured outputs also matched exactly. This is allocation evidence for that fixed postprocessing input, not a full-model peak or an OOM guarantee.

The prior CPU regressions passed at this unchanged head; they were not rerun for the GPU check:

python -m pytest tests/modular_pipelines/minimax_h3/test_modular_pipeline_minimax_h3.py -q -k TestMiniMaxH3VideoDecode

Dependencies came from a private, previously qualified overlay; its Triton 3.8, cuDNN 9.24 and NCCL 2.30 differ from PyTorch's exact pins. No packages were changed during the run. Full-size checkpoints, offload behavior, throughput and media quality remain unvalidated.

Codex assisted with implementation, review, validation and this description.

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[LeslieWylie]

@codex review

I changed decoded-video postprocessing in 6280cd9a to run in frame batches. I want frame order, pixel arithmetic and NumPy/PIL/tensor return types to stay the same; please check the partial final 16-frame batch and that tensor outputs stay on their original device.

The CPU checks cover the real tiny VAE and processor in FP32/FP16/BF16 with both normalization settings. The allocation figure refers to one CPU tensor's storage; full-size, offload and CUDA validation remain pending.

[LeslieWylie]

Added CUDA validation for the unchanged head 6280cd9a against b800f828 on one L20. The real tiny VAE and production modular decode/VideoProcessor path give identical full outputs across all three dtypes, all three output formats and both normalization settings, including the final partial batch.

A separate fixed-decoded postprocessing check also matches exactly. Total CUDA peak allocation is 90.94 → 30.19 MiB for NumPy/PIL and 90.94 → 72.57 MiB for tensor output. The description records the input shape, measurement boundary, dependency deviations and remaining full-checkpoint/offload/quality limits. This does not measure the full VAE or establish an OOM guarantee. Codex assisted with the run and comparison.