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Brac University
- Bangladesh
- intisar.ris
- https://www.linkedin.com/in/intisar-ahmad-eee/?isSelfProfile=true
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Joined
Oct 23, 2026
Popular repositories Loading
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bitconveyor-siso16
bitconveyor-siso16 Public16-bit bidirectional shift register with parallel load in Verilog. Verified with a self-checking testbench, fitted in Quartus and synthesized in Cadence Genus at slow and fast PVT corners to compar…
Python 1
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alu-16bit-vhdl
alu-16bit-vhdl Public16-bit ALU in VHDL with FSM Booth multiplier, restoring divider, flag unit and built-in self-test. Simulated with GHDL, synthesized for Artix-7.
VHDL
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EEE383-Dual-Sensor-Seismic-Alert-System
EEE383-Dual-Sensor-Seismic-Alert-System PublicDual-sensor hybrid seismic alert system: piezo and MPU-6050 sensing on ESP32 with RMS and FFT detection and ESP-NOW alerts. Two custom PCBs, firmware, MATLAB and Proteus validation.
C++
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evm-atmega32-voting-machine
evm-atmega32-voting-machine PublicSecure electronic voting machine on the ATmega32 with keypad, buttons and LCD. CodeVisionAVR C firmware, Proteus 8 simulation.
C
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lab-electrical-layout-bnbc
lab-electrical-layout-bnbc PublicElectrical service design of the LASSET laboratory (Room 12B-16L): three layouts, BNBC 2020 load calculations and an independent protection audit. AutoCAD drawings with Python calculation checks.
Python
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