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ux(studio): consolidated ABC shortcuts, truthful SV timing and native dark-control cleanup - #195
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Reviewed commit: 2130b41124
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| : panel.device.smpSynchMeasured | ||
| ? "MEASURED SYNC FLAG · verify sample-phase evidence independently" | ||
| : "FREE-RUN / UNQUALIFIED · PTP packets do not prove SV sample lock" |
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Do not label clock acquisition as free-running
When a TIME_RECEIVER is ACQUIRING, smpSynchMeasured remains false until enough qualified samples establish lock, but PtpClockDiscipline::observe() is already issuing phase or frequency corrections. This branch therefore displays FREE-RUN for a clock that is actively being disciplined, potentially misleading an operator assessing timing behavior; use only UNQUALIFIED here or derive the wording from ptpDiscipline.
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Exact-head acceptance matrix · consolidated GUI commit
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Merged release checkpoint: GUI-only PR #195 passed exact-head Qt, Windows Lifecycle and Native Preview/Inno checks at |
Unified operator GUI checkpoint — one tested PR
Base:
main@bcbebc32. Exact combined head:69cae271d044b32c03cc12fceac9257c0bf75f96.Merged PRs #192–#194 already supplied actual native Source/Follower/Monitor + PTP switch, the
smpSynchlab simulator, core Equal ABC / Balance angle operations, and the Studio/Inno icon. This PR reuses, not reinvents, that functionality.Changes included
Equal Value/Equal Angle/Balance Angle · 120°context menu wording plus right-click hints in magnitude and angle fields.smpSynch: measured flag is not automatically proof of PTP-to-sample phase lock; free-run and simulated flag remain distinct.Exactly five QML files, zero C++/embedded code changes. PTP, SMV, firmware updater and serial session have unchanged control semantics. Public v0.1.1 remains the physical stable baseline; experimental firmware clock discipline (#154/#162) is a separate acceptance track.
CI discipline
All four dark-control files were applied as one atomic commit on #195. Evaluate Qt/QML build+session harness, Windows lifecycle and the native Windows/Inno preview from the same exact combined head. Avoid rerunning old single-PR-head checks, redundant builds or launching a new pipeline for comments/doc-only edits. Review visual Windows rendering and physical ESP32 controls separately; CI cannot establish clock phase lock. Do not merge until exact combined head has required green gates.