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ux(studio): consolidated ABC shortcuts, truthful SV timing and native dark-control cleanup - #195

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masarray merged 2 commits into
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fix/studio-simulation-context-discoverability-20261016
Oct 16, 2026
Merged

masarray merged 2 commits into
mainfrom
fix/studio-simulation-context-discoverability-20261016

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@masarray masarray commented Oct 16, 2026 •

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Unified operator GUI checkpoint — one tested PR

Base: main@bcbebc32. Exact combined head: 69cae271d044b32c03cc12fceac9257c0bf75f96.

Merged PRs #192–#194 already supplied actual native Source/Follower/Monitor + PTP switch, the smpSynch lab simulator, core Equal ABC / Balance angle operations, and the Studio/Inno icon. This PR reuses, not reinvents, that functionality.

Changes included

  1. Discoverable Equal Value / Equal Angle / Balance Angle · 120° context menu wording plus right-click hints in magnitude and angle fields.
  2. Read-only SV timing interpretation next to simulated smpSynch: measured flag is not automatically proof of PTP-to-sample phase lock; free-run and simulated flag remain distinct.
  3. Consolidated former PR fix(studio): finish native dark-control readability in signal and firmware workflow #196 into this PR without a second integration/installer candidate:
    • shared dark checkbox for 3-phase link and per-channel enable;
    • shared dark Quality preset selector;
    • shared dark Firmware COM port selector and removal of duplicate local dropdown implementation.

Exactly five QML files, zero C++/embedded code changes. PTP, SMV, firmware updater and serial session have unchanged control semantics. Public v0.1.1 remains the physical stable baseline; experimental firmware clock discipline (#154/#162) is a separate acceptance track.

CI discipline

All four dark-control files were applied as one atomic commit on #195. Evaluate Qt/QML build+session harness, Windows lifecycle and the native Windows/Inno preview from the same exact combined head. Avoid rerunning old single-PR-head checks, redundant builds or launching a new pipeline for comments/doc-only edits. Review visual Windows rendering and physical ESP32 controls separately; CI cannot establish clock phase lock. Do not merge until exact combined head has required green gates.

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📝 Code Review ✅ Completed 2026-10-16T10:56:08.669526Z 2130b41 PR opened
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💡 Codex Review

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Reviewed commit: 2130b41124

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Comment on lines +59 to +61
: panel.device.smpSynchMeasured
? "MEASURED SYNC FLAG · verify sample-phase evidence independently"
: "FREE-RUN / UNQUALIFIED · PTP packets do not prove SV sample lock"

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P2 Badge Do not label clock acquisition as free-running

When a TIME_RECEIVER is ACQUIRING, smpSynchMeasured remains false until enough qualified samples establish lock, but PtpClockDiscipline::observe() is already issuing phase or frequency corrections. This branch therefore displays FREE-RUN for a clock that is actively being disciplined, potentially misleading an operator assessing timing behavior; use only UNQUALIFIED here or derive the wording from ptpDiscipline.

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@masarray masarray changed the title ux(studio): discoverable ABC Equal/Balance and truthful SV time quality ux(studio): consolidated ABC shortcuts, truthful SV timing and native dark-control cleanup Oct 16, 2026

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Exact-head acceptance matrix · consolidated GUI commit 69cae271

CI (one head, no re-runs unless failed): Qt/QML build + deterministic harness + headless/high-DPI launch; Windows close/reopen & serial ownership; native Windows preview installer clean install/upgrade/uninstall and NSIS-to-Inno migration; application + setup icon evidence.

Operator GUI test (Windows physical preview):

  1. Start with 4I/4V; right-click the Ia/U a magnitude field; Equal Value sets A/B/C only, preserving N and quality.
  2. Right-click phase B or C; Equal Angle copies clicked angle to A/B/C; Balance Angle · 120° leaves the clicked phase as the anchor, with other phases ±120°. Verify while output stopped and running.
  3. Check legible quality preset popup, the 3-phase link and individual channel checkboxes, and Firmware COM-port dropdown in Windows dark mode at 100% and high DPI.
  4. PTP OFF → Source → Stop → Follower/Monitor (with a real lab GM when available); verify displayed PTP RUNNING follows board ACK/telemetry and rejected command does not falsely latch ON.
  5. Switch SV smpSynch AUTO/0/1/2; inspect copyable diagnostics and on-wire metadata. Simulated 1/2 do not prove PTP↔SV phase discipline.
  6. Retain public v0.1.1 working installation as the device-flash baseline; use preview in a separate install location until bench acceptance.

Important actual code boundary: Main.qml::sendLinkedGroup() serially submits three requestSetSignal() commands. GUI group operations are convenient and ordered, not atomic at an SV sample boundary; an error can leave partial setpoints pending. A future transactional batch requires deliberate firmware/serial protocol design plus deterministic tests, not three UI writes disguised as atomic. Track as separate engineering hardening, not a blocker for a truthful GUI-only preview.

Unfinished timing work: issues #154/#162, actual continuous smpCnt-to-PTP epoch phase lock/hardware evidence/IED acceptance. No change to this in this PR.

@masarray
masarray merged commit ce92154 into main Oct 16, 2026
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Merged release checkpoint: GUI-only PR #195 passed exact-head Qt, Windows Lifecycle and Native Preview/Inno checks at 69cae271; squash merge main@ce92154c then passed post-merge Qt+Windows Lifecycle+Naming checks. Native preview artifact (operator lab, not public stable release): https://github.com/masarray/arstack61850/actions/runs/38891715452/artifacts/12042836148 . Keep proven v0.1.1 install and board-flash baseline separate. Missing physical operator visual UAT, board serial/PTP/SV acceptance, sampled-clock lock proof; do not conflate simulator smpSynch 1/2 with actual lock. Next CI optimization #199 separate.

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