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masarray
arstack61850
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P0: enforce shared IEC 61850-9-3 PTP SOURCE profile before START; truthful toggle
- #265
#265
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masarray
wants to merge 16 commits into
fix/p0-ptp-start-firmware-provenance-20261020
masarray/arstack61850:fix/p0-ptp-start-firmware-provenance-20261020
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fix/p0-ptp-profile-contract-20261020
masarray/arstack61850:fix/p0-ptp-profile-contract-20261020
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P0: enforce shared IEC 61850-9-3 PTP SOURCE profile before START; truthful toggle
#265
masarray
wants to merge 16 commits into
fix/p0-ptp-start-firmware-provenance-20261020
masarray/arstack61850:fix/p0-ptp-start-firmware-provenance-20261020
from
fix/p0-ptp-profile-contract-20261020
masarray/arstack61850:fix/p0-ptp-profile-contract-20261020
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Commits
Commits on Oct 20, 2026
feat(ptp): shared IEC/IEEE 61850-9-3 SOURCE cadence admission for Studio and firmware
masarray
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afd4250
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fix(ptp): fail preflight locally on mismatched 61850-9-3 SOURCE profile, before issuing serial commands
masarray
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4ff9cd3
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fix(studio): enforce SOURCE profile contract and display PTP STARTING without misleading toggle bounce
masarray
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7a3e862
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ux(studio): amber PTP switch pending state, green only for real board RUNNING
masarray
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518e227
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feat(ptp): expose compact read-only profile-rejection reason
masarray
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597c4d0
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fix(ptp): classify profile admission failures without changing time-critical PTP/SV
masarray
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795bea4
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fix(ptp): report actual firmware configuration rejection code to Studio
masarray
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d822728
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fix(ptp): PTPROLE rejection uses firmware-owned cause
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25818c3
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test(studio): reject SOURCE Pdelay/cadence mismatch before PTP serial state machine
masarray
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24c64db
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test(ptp): confirm identical portable 9-3 admission from scalar Studio and runtime options
masarray
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2908e7f
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test(studio): guard stable switch and board-specific PTP configuration causes
masarray
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654dd42
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test(studio): update advanced PTP profile contract for explicit SOURCE role parameter
masarray
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836c881
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ux(studio): preserve amber PTP STARTING intent in both Main tray and Advanced, no immediate switch snapback
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0835dae
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ux(ptp): lock SOURCE cadence to 1s in standard Studio profile; keep core/backend validation for direct calls
masarray
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ef4de7a
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test(studio): standard SOURCE cannot accidentally send nonstandard hidden cadence
masarray
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ce5ffac
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ux(ptp): hide SOURCE-only non-editable timing fields, show one true 9-3 profile summary
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df73fea
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