[masarray]

⛔ RELEASE HOLD — PHYSICAL REGRESSION; CURRENT #286 IS NOT A SHIPPABLE RC (2026-10-23)

Do not merge into main, mark stable, ship the 042df0d4 package, or use previous Native Preview green status as a physical no-regression claim. The operator observed that the paired 042df0d40ddd3f061ebeebc81c662c585827e346 build no longer delivered SV readable by ARSAS/DigSubAnalyzer. The actual earlier 35s / 140,271-frame valid PCAP's buildId was 7c95f70cced4d126 (not 73c97272 or 042df0d4). The exact failure mechanism remains unknown until new SVLIFE/START diagnostics and PCAP; no malformed-wire assertion from a STOPPED/header-only capture.

Active parallel team recovery: Draft #288 starts from immutable-intent checkpoint/pcap-proven-sv-ptp-7c95f70c-20261023 (7c95f70c) and ports Studio AUTO-LIVE controls plus its tests, with narrowly scoped CI workflow/routing changes. At reviewed 90e2755f1412d7b959b4403653f818a16ea70bb6, compare against 7c95 is 5 commits ahead, 0 behind, changing 5 files (Main.qml, WorkflowBar.qml, operator check, ESP32 workflow, routing checker); firmware/PTP/COM runtime source files are unchanged. Firmware newly rebuilt from unchanged sources still needs real-board verification. Its Native Preview workflow was IN PROGRESS when audited; do not advertise #288 as physically accepted.

Stage→Main decision: #286 remains an integration/preservation reference only; #288 is the current recovery test lane, not automatically promotable into main. Full exact-head CI, matched Windows installer/BIN, first-30s live wire capture with DigSubAnalyzer+ARSAS, AUTO sync, subsequent IA/UA/frequency edits while continuously RUNNING, and physical SIPROTEC PTP LOCKED + SV reception are mandatory before release consideration. Do not close #284 external-GM failover or unrelated Workbench/Simulator PRs as collateral. Main and checkpoint branches remain untouched.

Important: Older paragraphs below are historical checkpoints (including “Native Preview SUCCESS” and “Current exact HEAD” descriptions). They are not the current release authorization.

---

LIVE P0 UPDATE · 2026-10-23 · no main merge

Current exact HEAD 73c97272fb1381badcd637a8a3954ee9365a1dc4 · Native Preview run 39879242493. Native Preview SUCCESS on exact HEAD: firmware ESP32-P4 and Windows x64 Inno installer jobs both succeeded in run 39879242493. Session/clipboard/capture harness, native GUI smoke and Windows upgrade/uninstall acceptance passed in that workflow. Other Draft-routed full suites skipped; hardware FAT remains open. Artifact installer SHA256 104a52f4a47dacab93266de722460c2cc2080c213084e551a3c34b6d6e17798c; ESP32 pre-v3 firmware SHA256 53818689fa06cfacfe8824fa867e371889f1a8ac7fe362dc1e79b4a996b339b8.

Commits on canonical Draft PR #286:

• 773a320: missed SHOW health probes mark control degraded without closing live COM and killing 700ms heartbeat; real serial transport failures remain authoritative.
• ce4531a: firmware START accepted now includes board STOP sequence, Studio rejects pre-START stale STATE=STOPPED or SVLIFE before verified START and accepts later incremented STOP.
• 5dc4b11: debounce one 750ms false COM enumeration miss to 2.25s before disconnect; no delay on genuine QSerialPort failure.
• 73c9727: capture STOP counter before g_running=true to avoid watchdog/ACK race.
• Added deterministic Studio regressions for each host failure path in existing harness. Existing PTP GM/SV clock architecture and RUNNING 4I4V atomic CFG paths preserved. Firmware manifest image uses exact HEAD, pre-v3 ESP32-P4 only.
• User capture from older fix(SV/PTP): fast real AUTO synchronization to own PTP GM without 10-epoch delay #284 c0f3b4e3: ~4000 fps 30s with 0 missing/malformed; smpSynch=0→2 at 4.25s. START drop not recorded, so true field root cause remains unproven pending exact-build STOP event diagnostics.
• Preservation-ledger graph triage across all 36 open PRs: integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286 remains canonical Draft; feat(SV P0): SCL-preserved IEC Ed2.1 4I4V smpRate/smpMod wire profiles #285 and Release blocker: eliminate ESP32-P4 START timing misses #92 have 0 exclusive source commits (ancestry-contained in this exact HEAD), but do not close until their metadata/wire and physical acceptance gates are explicitly dispositioned; fix(SV/PTP): fast real AUTO synchronization to own PTP GM without 10-epoch delay #284 is diverged with 17 source-exclusive commits, including the real external-GM AUTO actuator absent in integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286. The other 32 open source PRs are diverged, many unrelated Workbench/Simulator lanes, and must not be closed on title similarity. Current inventory: 36 open PR / 24 open issues; no source PRs closed in this session. Independent PTP troubleshooting #287 external-board issue retained.
• NOT ACCEPTED: SIPROTEC relay PTP LOCKED / Pdelay receiver capture / 4I4V relay channel readings / 300s or 1h physical STOP soak. Do not merge main, delete unique source branches, or release stable without explicit approval.

---

2026-10-22 HARDWARE DEBUG STATUS · AUTHORITATIVE

Current exact head: 7c7032e182f5412548baafbdb876765620ca10cf. PR stays DRAFT; DO NOT MERGE and never promote untested software as SIPROTEC acceptance.

• Physical user PCAP of older c0f3b4e3: 121,383 SV frames over 30.346 s at 3999.91/s, no missing/duplicate/malformed; simulated bench smpSynch=0→2 at 4.25s and stays 2 for 104,383 samples; 35 Announce/Sync/Follow_Up each. No mid-capture wire STOP; red START-button collapse cause not proven and may be outside capture or a GUI/readback issue. Board's earlier flight ETHERNET_LINK_LOSS record is historical; newer ACQUIRED is present.
• Actual diagnostic code committed a59b11b2: Studio automatic UTC serial/heartbeat/START/STOP/error log to Windows AppLocalData Diagnostics (8MB+previous), UI warning traceback, unexpected STOP forensic SHOW for board SVLIFE; UI Open log folder and Copy diagnostics.
• Existing Preview workflow had malformed duplicated publication YAML; restored proven preview-only build without any prerelease publication (84f013c2). A single purpose-built Draft integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286 firmware build exception guarded in CI routing (7c7032e1) so the native Windows preview can produce exact-head GUI + ESP32 binary even while PR remains Draft. Build results must be checked; until then, do not claim latest diagnostic EXE tested.
• Known divergence: integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286 is not descended from fix(SV/PTP): fast real AUTO synchronization to own PTP GM without 10-epoch delay #284: 17 exclusive fix(SV/PTP): fast real AUTO synchronization to own PTP GM without 10-epoch delay #284 commits (including actual ESP32 external-GM AUTO supervisor and Studio UI) are NOT yet integrated into integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286. Other 45 branch-only changes must be preserved; no blind merge or PR closure. Opt-in external failover is secondary to primary simulated-GNSS bench SOURCE.
• Direct test requirement: simulated GNSS-like PTP GM and SV share ESP32-P4 IEEE1588 timebase, SIPROTEC 5 reports PTP LOCKED and consumes synchronized 4I+4V SV. No GPS/standalone PTP server mandatory in this simulation. Bench metadata must not be interpreted as real-world UTC traceability.

---

CURRENT CODE STATUS · 2026-10-22

#253 atomic RUNNING 4I4V code is now ported, but software CI + physical FAT are NOT complete. Last code SHA b4a11c60833d6ad3a2ab514715344917f188f440, documentation checkpoint 011ff12ed0fcb6f1a8c25fe6b67d43cf1af612ec. Firmware RUNNING CFG, Studio Apply live/readback, no START reset, error preservation, and regressions are committed. Exact code CI: ESP32-P4 SMV Injector SUCCESS, other checks still running or canceled at snapshot. Installer direct EXE has NOT been verified. Do not merge main or close #253 yet.

Start here — canonical current handoff.

---

Integration gate — CURRENT (2026-10-22)

Single DRAFT PR now targets main to consolidate the complete Studio + ESP32-P4 PTP/SV code lineage without 27 chained GitHub merges. Main has NOT changed. This draft is NOT ready to merge or a hardware-qualified release.

START HERE: safe-merge handoff, current status and strict blockers.

Last compiled software-code SHA: b6c13a5e87fae89b9258834cefae2cec8be5f1c4 with all 11 observed GitHub PR workflow results SUCCESS (C++ CI Linux GCC/Clang/Windows MSVC, ESP32 firmware PTP/SV, Studio Qt, IED Simulator Qt, core, embedded, security, routing, naming, interoperability). Latest additional commit 23a99cafd202e7eeae357cfea0c11fee60b7f7de changes only documentation, no compiled code. CI does not establish any hardware or installer pass.

Source preservation repairs: 49877470e34bf2883ec60e7c8dd0b758a910c51c restores #251 stale-transaction bank-generation refusal; b6c13a5e87fae89b9258834cefae2cec8be5f1c4 restores #248 multi-reader lock-free bank (fixes sentinel), C++ two-reader stress regression.

Blocking final merge: #253 running 4I4V atomic live transaction missing; #249 live frequency/editor pendingApply gate audit; true ESP32/Studio AUTO_FAILOVER actuator; actual SIPROTEC FAT with physical Pdelay, sync and currents; exact SHA native Smart Inno .exe + firmware and Windows lifecycle; proper GitHub main protection and explicit merge review; 21 alternative/16 independent PRs tracked not discarded. Never close PRs purely based on shared names.

Source inventories: 64 PR +26 issue ledger and 37 branch divergence review.

---

READ FIRST — durable no-loss handoff (2026-10-22)

START HERE: ARStack61850 preserved progress, frozen PR SHAs and next-thread procedure. Machine manifest covers all 64 open PRs + 26 issues; all 21 sibling branches have per-file source/tip blob checks (179 touched path occurrences), all 16 independent PRs have full changed-path inventories (235 occurrences), each record retains exact original PR SHA.

Preservation is not semantic parity: 7 alternate-branch paths absent from tip, 26 independent-file occurrences absent from PTP tip, and 169 different side branch blob occurrences require explicit per-feature audit; never blindly cherry-pick or close source PRs. #256 two non-ancestor commits need receiver fail-closed parity proof. Integration auditor is read-only and CI Routing Policy validation + Product Naming Guard completed green on exact docs HEAD 0f75394f83f5501c1a2371fc4780a78941e36cb9 (draft skips expensive build jobs).

Safe boundary: #285 88575b874f35827afa54c86f294e11a798f6b8ae remains the untouched physical-test candidate. No main merge, no source PR close/delete, no physical relay FAT claim, no direct .exe published assertion. AUTO_FAILOVER remains portable policy-only until integrated on the actual board.

---

Scope: ARStack only, stacked on PR #285

Deterministic source-selection policy core. Does not yet claim board-integrated AUTO_FAILOVER.

• Explicit INTERNAL_GM, EXTERNAL_FOLLOWER, AUTO_FAILOVER with bounded acquisition/loss deadlines.
• No selected external means internal begins immediately; selected EXTERNAL_FOLLOWER never silently falls back.
• Opt-in fallback revokes SV claim and pauses TX, stops receiver, requires exclusive EMAC cleanup, refuses competing GM, re-arms at measured whole second after GM identity matches.
• Optional restoration requires independent external-candidate verification.
• Deterministic regression in tests/test_ptp_runtime.cpp, no changes to fast SOURCE path.

Missing hardware actuator

ESP32 ptp_mode_facade integration, Studio configuration transport, external GM identity pinning and physical second-boundary action remain PENDING. No GUI fake AUTO control and no claim of SIPROTEC FAT.
Do not merge main or stable.

Canonical consolidation audit (2026-10-22)

Preservation ledger: all 64 open PR heads, 26 issues, 27-chain/21-side/16-independent mapping, branch-ancestry counterexamples and no-regression gates. The ledger is audit status only, not proof that every side PR's unique behavior is merged. No main merge or hardware certification. Main remains unprotected in branch API and must have protections configured before convergence.

Integration blocker: audit side-branch unique changes (#251/#253/#248 etc.), finish actual ESP32/Studio PTP AUTO_FAILOVER actuator and physical SIPROTEC acceptance. Do not close the other PRs without a verified per-PR disposition.

---

BENCH TARGET — ESP32-P4 AS SIMULATED GLOBAL GM

Engineering requirement clarified from physical tester's 2026-10-22 capture/feedback. Do not regress or reinterpret the testbench as requiring an external GPS/PTP server. The ESP32-P4 deliberately runs an isolated simulated GNSS-quality PTP GM from its own IEEE1588 MAC timebase; its 4I+4V SV must align smpCnt / second epoch to that very same clock. The SIPROTEC 5 is the PTP receiver; its actual LOCKED status and ability to consume SV in sync are the primary acceptance criteria.

• Preserve the explicit Studio 'Relay test bench · Simulated GNSS PTP Grandmaster' (benchGlobalGm) mode and its GNSS-like on-wire Announce parameters clockClass=6, timeSource=GPS, traceability flags as simulated test stimuli, not real GNSS hardware claims. Preserve smpSynch=AUTO -> 2 when the same PTP-SV MAC/phase qualification has passed. Do not arbitrarily downgrade this explicitly selected simulator to local 1 or require an external reference before advertising the desired simulated global state. Never force 2 as a substitute for missing PTP-SV phase alignment.
• PTP SOURCE has no upstream discipline; a SOURCE-side UNLOCKED receiver-servo field alone cannot be treated as proof the relay is not locked. Verify relay's own PTP status, selected GM identity, Pdelay exchange when visible, SV synchronization and actual 4I+4V magnitudes/phases.
• Direct primary test: ESP32-P4 isolated Ethernet to SIPROTEC 5 (switch/mirror optional); SOURCE bench GM START → synchronized SV 4000 fps at 50Hz with correct VLAN/SVID/APPID/smpRate/smpMod/smpCnt → SIPROTEC locks to ESP32 PTP and accepts the SV stream without time/quality alarms. Use original physical packet capture and relay diagnostics. Independent GPS/UTC/PPS reference not a prerequisite to this single-GM lab acceptance; a separate production standards/traceability certification would require its own evidence.
• Recorded earlier physical capture on firmware 3ca1ff9d06d3: approximately 488,595 SV frames in 122s, no missing smpCnt/duplicates/malformed, ~4000 fps, PTP Announce/Sync/Follow_Up present, transition smpSynch=0 → 2 observed. Treat these as capture evidence, not proof that latest #286 SHA was run or that SIPROTEC accepted it. The smpCnt=998 flag transition is not by itself a sample-counter error or standards failure.
• AUTO_FAILOVER for other external Grandmasters is secondary and optional, not a prerequisite for the principal INTERNAL/Simulated GM test. No new PRs/issues for reiterating this target; keep existing consolidation integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286 draft until audited code, exact-head installer/firmware and real relay evidence are ready.

[masarray]

PR/issue housekeeping checkpoint · 2026-10-23

Canonical Draft integration remains #286 at 042df0d40ddd3f061ebeebc81c662c585827e346, no main merge or branch deletion. This note records actions, not a physical FAT claim.

Closed as superseded (source code preserved, NOT merged to main):

• feat(SV P0): SCL-preserved IEC Ed2.1 4I4V smpRate/smpMod wire profiles #285 88575b874f35827afa54c86f294e11a798f6b8ae: exact ancestor of integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286 as verified on head 8c58e738 (0 source-exclusive commits); Ed2.1 SCL SV metadata remains in the integration source. Physical relay acceptance transfers to integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286.
• Release blocker: eliminate ESP32-P4 START timing misses #92 acd81524d59bd670f1ea2805ac755f5c1f34d6d5: exact ancestor of integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286 as verified on head 8c58e738 (0 source-exclusive commits); previous timing fixes retained. 10x START/STOP, first-bucket counters and 1h soak remain unaccepted and tracked through integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286.

Closed duplicate issue, acceptance preserved:

• P3: integrate trusted-SCL initial snapshot into IED Connection workspace #87 marked duplicate of open P3: wire trusted SCL-assisted connect into Workbench product path #88, after transferring the unique missing/extra-domain, SCL provenance, fail-closed, session-generation and strict Qt/Windows QA criteria into P3: wire trusted SCL-assisted connect into Workbench product path #88. P2 core issue P2: deterministic SCL-assisted MMS connect and initial FC-root snapshot #85 stays independent.

New operator bench observation: local simulated-GM SV/PTP synchronization reported ≤10 seconds. Earlier physical PCAP of firmware c0f3b4e3 measured smpSynch 0→2 at ~4.25 s. Updated open issue #154. This does not prove current commit's SIPROTEC PTP LOCKED, Pdelay, SV channel acceptance, or unexpected START-stop root cause.

Deliberately retained: #284 (17 source-exclusive commits / actual external-GM AUTO failover actuator absent from #286), #250/#251/#248/#249/#253 (historical branches diverged, full semantic/exact physical parity remains to audit), #279 and separate Workbench/Simulator work. Closing ancestry-contained PRs is not permission to sweep independent behavior. Current search snapshot: 34 open PR, 23 open issues.

[masarray]

2026-10-23 AUTO-LIVE exact HEAD SOFTWARE CI PASS — Release candidate only.

Exact commit 042df0d40ddd3f061ebeebc81c662c585827e346, Native Preview run https://github.com/masarray/arstack61850/actions/runs/39882032904: firmware job SUCCESS, Windows-preview job SUCCESS. All explicit jobs passed: SOURCE PTP–SV no-flap regression, ESP-IDF 5.5.4 firmware, native Qt/session build, packaged GUI smoke / SHA firmware contract, Inno clean install, running-app hot upgrade, clean uninstall, real historical NSIS v0.1.1→Inno migration. Artifact firmware #12470928004, Windows Setup/Portable artifact #12471142203. Extracted Setup SHA-256 8a669a8ea0e677724a88ea7f66e948e3e5ba0dfe3f0eda4886ed630c3478ad74; ESP32-P4 BIN SHA-256 04a91d4325eb8fd6f7fde205accd65c7afb382c53a838a26a2043dfee2c1da91 (531824 B), identical to bundle manifest; portable SHA 5af3b964323742be1a64c5f0178251ca995e351e377204fb118aa19b4cb40ac7. Code diff from lab checkpoint touches only Studio Main.qml, WorkflowBar.qml and GUI structural regression test — no PTP, SV, or embedded publisher code modifications.

New recovery checkpoint branch checkpoint/auto-live-rc-ci-pass-20261023 at exact CI green SHA. Earlier field-tested baseline preserved at checkpoint/sv-ptp-digsub-auto-7s-20261023 / 73c97272....

OPEN PHYSICAL FAT: operator must validate Enter/focus-out IA/UA live on wire without STOP/START and with stable PTP/SV (existing DigSubAnalzyer ~7s), plus SIPROTEC 5 LOCKED/4I4V relay measurements for declared relay-ready stable. No release-stable promotion or main merge yet. Draft #286 remains open; no destructive cleanup of source PRs.

[masarray]

Release hygiene + team-safe triage · 2026-10-23 · checkpoint

Authoritative read-only source snapshot for this cleanup: canonical Draft PR #286 head 042df0d40ddd3f061ebeebc81c662c585827e346, base main, NOT merged. No code files, branches, main, GitHub workflow definitions or other lane's QML changes were modified. Other thread owns AUTO-LIVE Main.qml / WorkflowBar.qml / operator tests and preserved physical checkpoint checkpoint/sv-ptp-digsub-auto-7s-20261023 plus exact-CI checkpoint checkpoint/auto-live-rc-ci-pass-20261023. Do not rebase/reset/delete checkpoints.

Disposed in this cleanup

• CLOSED as intentionally superseded Studio UX variants: P0 Studio UX: exact 4I+4V START, vertical matrices, default PTP and centered controls #236, P0 Studio UI polish: exact table-to-SV START, stacked 4V/4I, readable controls #237, Studio P0 UX: always send visible 4I+4V on START; stacked tables and control polish #238, Studio P0: preserve SV/PTP milestone; exact 4I+4V START snapshot and polished operator layout #240, P0 Studio UX: authoritative 4I+4V START, compact vertical layout and readable controls #241. Original source-head SHA and feature-level replacement evidence are in each PR's closing comment. These branches are diverged, not claimed merged/patch-equivalent; older overlapping 4I4V START layouts are superseded by new atomic scenario/readback + vertical Studio UI. No branch deletion, no changes to the active AUTO-LIVE implementation.
• CLOSED duplicate tracking: issue Milestone R0.1 — Compact ARStack Browser workflow and 1024px layout QA #135 R0.1 compact Browser. Transferred all pending 1024px/normal width, canonical Browser, quality/time and physical evidence conditions plus historical CI to OPEN parent issue Milestone R0 — Restore usable IEC 61850 Browser before UX expansion #128 before closure; not a completed R0 gate.
• KEPT OPEN with explicit review note: P0 Studio operator UX: table-as-wire SSOT, visible injector title, stacked 4I+4V, centered controls #239 requires on-toggle live three-phase value changes, whereas integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286 toggle is currently preference-only; semantic parity must be reviewed, not lost in blanket closure. All independent Workbench/Simulator PRs remain separate.
• Updated OPEN issues: P3-A1.1: live SV signal control without realtime stream rebuilds #42 retains hardware atomically-applied live-setpoint FAT after AUTO-LIVE software CI; M2: continuously PTP-disciplined SV timeline, truthful smpSynch and IED sync-alarm acceptance #154 records current user/team DigSubAnalyzer + ARSAS acceptance (~7sec, 35sec PCAP 140,271 SV, 105 PTP, 3999.887 fps, zero counter gaps/BER defects). Avoid interpreting older header-only PCAP as current test results.

Current issue/PR inventory

29 OPEN PR / 22 OPEN issues (was 34 / 23 at start of this cleanup; was 36 / 24 before previous cleanup). Since cleanup work began previously: 7 PR + 2 issues closed total. This pass itself: 5 PR + 1 issue.

Exact-head CI snapshot — not physical qualification

At 042df0d40ddd3f061ebeebc81c662c585827e346: Native Preview run 39882032904 SUCCESS with both firmware / build-esp32p4 and windows-preview jobs SUCCESS, including native GUI test, matching firmware image, Inno installer clean installation/upgrade/uninstall per build team's record. Separate CI Routing Policy and Product Naming Guard SUCCESS. 11 other required full workflows SKIPPED under Draft; do NOT call entire CI green.

Release hold — explicit remaining gates

1. Studio AUTO-LIVE physical truth: on matched 042df0d40ddd3f061ebeebc81c662c585827e346 installer/BIN, edit IA amplitude/phase and UA amplitude/phase with SV already RUNNING. Press Enter, Tab, click away; observe automatic ACK/readback and actual 4I4V on-wire update without Apply Live button or STOP/START/PTP reset, smpCnt gaps or frequency drift. Preserve serial/PCAP and analyzer readings.
2. Primary IED acceptance: actual SIPROTEC 5 selected ESP32 simulated local Grandmaster, PTP LOCKED/Pdelay where applicable, accepts intended 4I4V SV and reported values/angles/quality, no unexpected sync alarm; document exact device and matched build, measured acquisition ≤10sec, plus START/STOP and longer running/soak.
3. CI/release: exact final source SHA, source-matched firmware+Windows EXE, remaining full C++ / security / Qt / firmware / Windows lifecycle / release policies must be run and PASS, not SKIPPED. Confirm clean/hot installer migration and no hidden old process for release candidate.
4. External GM P1 option: fix(SV/PTP): fast real AUTO synchronization to own PTP GM without 10-epoch delay #284 remains OPEN and diverged (17 exclusive commits), including real AUTO_FAILOVER device actuator not yet in integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286. Do not claim external-auto failover exists in shipped candidate; require deliberate scope exclusion/disable or verified integration with dedicated bench test before advertising this capability.
5. Other source lanes: P0 Studio: fix live GUI frequency and channel ENABLE delivery; define on-wire acceptance #249/P0 Studio: cancel queued SV START with bounded priority STOP and block bare START #250/P0 SMV: atomic 8-channel firmware scenario commit with token/hash ACK and verified START #251/P0-B: atomic running 4I+4V live setpoints with firmware commit/readback #253 (live/STOP/transaction branch-only differences), P0: make ARStack Studio shutdown deterministic on Windows #99 Windows lifecycle, fix(studio): truly compact 4I+4V, equal phasor/wave area and atomic input commits #279 Studio alternative, and all Workbench/Simulator lanes remain OPEN until feature-by-feature disposition. Do not close on same title, nor merge main based on software build alone.

Stable release NOT YET authorized. This note is an audit/disposition checkpoint and does not overwrite other workers' code or their hardware claims.

[masarray]

STAGE → MAIN · repository hygiene checkpoint · 2026-10-23

Canonical staging candidate: Draft PR #286, head 042df0d40ddd3f061ebeebc81c662c585827e346, base main@7f6b946cab8565f37c31b460463576a0bb1e3fc5; mergeable=true only means GitHub reports mechanical mergeability, NOT acceptance authorization. GitHub branch search found no branch literally named stage-main. Do not create/retarget one while other team lane owns the current integration. No main merge, no source-branch deletion, no modifications to AUTO-LIVE UI/QML.

Actual dispositions in this round

• 5 source PRs CLOSED as superseded, not merged: P1 Studio: checkbox-free 4I+4V tables and accessible 3-phase switch #255 (no checkbox, switch preference, disabled-preset migration), P0 SMV SSOT reliability: concurrent snapshot safety and fail-closed START #248 (4-bank multi-reader concurrency, 20k stress, fail-closed stop/start), P0 Studio: cancel queued SV START with bounded priority STOP and block bare START #250 (bounded priority SV and PTP STOP; bare START refused), P0 SMV: atomic 8-channel firmware scenario commit with token/hash ACK and verified START #251 (token/hash/boot/generation CFG commit + readback before START), P0 Studio: fix live GUI frequency and channel ENABLE delivery; define on-wire acceptance #249 (obsolete individual live SET/frequency gating replaced by atomic auto-live). All source heads DIVERGE from integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286: replacement behavior was inspected directly in current files and native regression suites, but branch-only commits were not claimed ancestry-contained or byte-for-byte integrated. Each PR has its original SHA and proof comments, branches intact.
• 1 redundant issue CLOSED as duplicate tracking: R1A — Signal Catalog and offline canonical DataSet Browser #131 R1A. Every OPEN requirement and historical fixture PASS was transferred into parent OPEN Milestone R1 — Open SCL and Discovery converge into verified static reporting #129, and R1B OPEN R1B — Static DataSet to exact RCB reporting workflow #134 now points to parent milestone, not completed R1A.
• KEEP OPEN with explicit release blockers: P0-B: atomic running 4I+4V live setpoints with firmware commit/readback #253 (AUTO-LIVE hardware IA/UA while RUNNING, no smpCnt/clock reset, commit/readback with real board); P0: make ARStack Studio shutdown deterministic on Windows #99 (Windows close→actual PID exit→immediate relaunch 2×, independent Windows Lifecycle CI not yet executed on this Draft SHA). fix(SV/PTP): fast real AUTO synchronization to own PTP GM without 10-epoch delay #284 real external-GM AUTO_FAILOVER actuator is a separate unmerged capability. P0 Studio operator UX: table-as-wire SSOT, visible injector title, stacked 4I+4V, centered controls #239 is not semantically redundant: switch activation behavior differs. Other Workbench/Simulator PRs were not touched.

Release gates as of current #286 head

Software checked: Native Preview 39882032904, Windows installer/native harness and firmware jobs SUCCESS at 042df0d40ddd3f061ebeebc81c662c585827e346; CI Routing Policy and Naming Guard SUCCESS. The other full CI workflows were SKIPPED under Draft; DO NOT count these as green. Installer/firmware must be regenerated if HEAD moves.

Physical: team field capture before AUTO-LIVE QML edits showed ~7s AUTO, 140,271 SV in 35s, zero missing/malformed, ARSAS/DigSubAnalyzer decode; this is an earlier field checkpoint, not a physical validation of latest AUTO-LIVE code. Before stable release: matched-board IA/UA live edit with device readback and PCAP showing no STOP/START/smpCnt reset/PTP rearm; SIPROTEC 5 receiver PTP LOCKED / selected GM / quality and 4I4V measured channels / no unexpected alarm; 10× START/STOP and prolonged soak; full exact-head CI; explicit merge approval.

Inventory verified after cleanup: 24 OPEN PR / 21 OPEN issues, down from 29/22 at the beginning of this round. This is housekeeping of preserved work, not engineering capability deletion or successful release. Cooperate via this PR discussion only; the separate active Studio thread owns AUTO-LIVE code/checkpoint branches.

[masarray]

RELEASE CANDIDATE WITHDRAWN — 2026-10-23 — observed field regression

Operator reports that the paired 042df0d4 AutoLive FAT package no longer produces SV readable by ARSAS/DigSubAnalyzer. Retract our earlier software-CI-green implication of no-regression. This is a P0 physical release blocker. Firmware ZIP and bundled Windows firmware are SHA-identical, so the delivered package was not accidentally a mismatched ZIP. However, the last PCAP with 140271 healthy frames actually reported buildId 7c95f70cced4d126, NOT 73c97272 or 042df0d4. Four commits between 7c and 73 include changed board START ACK (stop_seq) and host verification/COM reconnect; 042 adds only GUI auto-live. Those subsequent changes were not proven on wire by the attached PCAP. Consequently the prior checkpoint/sv-ptp-digsub-auto-7s-20261023 anchor at 73 was not the true capture-verified build.

The ACTUAL ORIGINAL known-wire binaries were downloaded from successful exact-head Native Preview run 39874249108 (Studio Windows artifact 12467757371, ESP32 firmware artifact 12467512907). Original ESP32 SHA256 8a78d5f91bc78cfab8f32248b20d081eca0300aa79eee3cb1d3683f7175778ce; Windows installer SHA256 1b88d9d41c88b1952743b89a724d8f3c357463f0116e6e65cfc65fee44f41e67. Full ZIP/portable firmware, manifest SHA identity verified. New immutable-intent recovery checkpoint checkpoint/pcap-proven-sv-ptp-7c95f70c-20261023 points at the actual captured source.

Isolated Auto-Live recovery PR #288 is Draft based on the exact 7c95 checkpoint with only three GUI + operator-test files changed; firmware production sources identical to actual captured commit. Await full matched Windows/firmware CI and fresh real-wire capture. The exact cause of the 042 failure (STOP vs session transport vs SCL/profile/NIC vs wire) is unproven without 042 device SVLIFE/START diagnostics and current PCAP; do not invent a malformed encoding conclusion. PLEASE NO MAIN MERGE, stable release, branch removal, or mass issue/PR closure.

[masarray]

Stage→Main PR/issue ownership map · 2026-10-23 · exact GitHub inventory

Team-safe scope: GitHub hygiene/release guard only; another thread owns #288 recovery sources. No code commit, no main merge, no branch deletion, no forced retarget/closure of a diverged source PR.

Important correction: previous RC #286 042df0d4 had a field-reported SV receive regression. The 35s PCAP/140,271 SV / ~7s AUTO proves 7c95f70c only. Its recovery path is Draft #288 90e2755f based exactly on this original captured source. PR #286 now starts with a RELEASE HOLD note; its earlier software CI green result cannot be used to advertise stable.

Open PR inventory: exactly 25, separated by executable release ownership

Lane	PRs	Disposition
Recovery vs rejected integration	#288, #286	P0 #288 fresh hardware and CI verification; #286 remains blocked integration history; do not merge either yet
PTP timing, receiver, external GM	#284, #256, #166, #157, #153	Preserve unique hardware phase/receiver/failover semantics; external-GM P1 #284 is not part of core simulated-GM P0 release unless separately validated and explicitly enabled
Studio UX, control, Windows lifetime	#279, #272, #266, #263, #259, #253, #239, #99	Keep divergent unique edits and their acceptance; #253 physical AUTO-LIVE and #99 close→PID exit→reopen are P0 release blockers; do not port older GUI patches across #288
Independent Workbench / Reporting / Browser	#230, #228, #219, #172, #164, #137, #136, #130, #127	Different product lane; preserve separately, do NOT close to make Studio metrics look better or merge into Studio firmware RC
Independent IED Simulator	#75	Separate simulator/external-client acceptance, not Studio SV release

Open issue inventory: exactly 21

• SV/PTP standards/runtime/field: M3: unified PTP–SMV context supervisor, continuous PPS↔smpCnt, dual clock authority and bounded recovery #162 M2: continuously PTP-disciplined SV timeline, truthful smpSynch and IED sync-alarm acceptance #154 P3-H: SMV standards invariants, deterministic WirePlan and recovery orchestration #139 P3-A1.1: live SV signal control without realtime stream rebuilds #42 P3-A0.1: tolerant SCL dialect normalization and vendor-extension quarantine #40 P3-A1: compiled SV device profile and deterministic ESP32-P4 activation #36 P3-A2: observed SV wire fingerprint and configured-vs-observed resolver #35 P3-A: vendor-neutral SCL-driven SV interoperability profile foundation #33 P3: standards-first SCL-driven SV profiles and IEC/IEEE 61850-9-3 PTP synchronization #24 P2: deterministic ESP32-P4 Sampled Values publisher and timing evidence #21 (10).
• External 3.2 hardware independent troubleshooting: PTP troubleshooting #287 (1). Do not flash a pre-v3 recovery image onto the v3.2 external reporter's board.
• Workbench/Browser/MMS/reporting: P0 Workbench Reports: verified SCL/MMS DO→DA hierarchy and semantic process values #226 R1B — Static DataSet to exact RCB reporting workflow #134 Milestone R1 — Open SCL and Discovery converge into verified static reporting #129 Milestone R0 — Restore usable IEC 61850 Browser before UX expansion #128 Field acceptance: P6 multi-IED, static reporting and passive MMS capture #124 IEC 61850 file-service golden parity: Directory/Open/Read/Close/Delete #96 IEC 61850 server golden parity: canonical hierarchy, semantic defaults, indexed RCB instances #95 P3: wire trusted SCL-assisted connect into Workbench product path #88 P2: deterministic SCL-assisted MMS connect and initial FC-root snapshot #85 Professional parity: readable URCB/BRCB root structures for external-client discovery #84 (10).

Pre-release Stage→Main stoplight

1. P0 STOP/NO-GO now: actual integration(RC · DO NOT MERGE): ARStack Studio + ESP32-P4 PTP/SV consolidated #286 package did not reproduce the earlier healthy SV subscriber capture; CHECKPOINT MERGE: Auto-Live and 5-file capture on PCAP-proven SV/PTP baseline #288 physical validation not yet supplied. New GUI/firmware artifact must be matched by exact buildId/SHA.
2. Source continuity preservation: checked on CHECKPOINT MERGE: Auto-Live and 5-file capture on PCAP-proven SV/PTP baseline #288 head: four-bank reader pin counts and stress regression, separate queue-full SV/PTP STOP lanes, full GUI 4I4V snapshot, CFG COMMIT/READBACK identity, no-checkbox table and migrated disabled presets, AUTO-LIVE coalesced edit path. Closed superseded PRs P0 SMV SSOT reliability: concurrent snapshot safety and fail-closed START #248/P0 Studio: fix live GUI frequency and channel ENABLE delivery; define on-wire acceptance #249/P0 Studio: cancel queued SV START with bounded priority STOP and block bare START #250/P0 SMV: atomic 8-channel firmware scenario commit with token/hash ACK and verified START #251/P1 Studio: checkbox-free 4I+4V tables and accessible 3-phase switch #255 need not be reopened solely due to 286 rollback, but source parity does not prove hardware parity. Ancestor PR heads feat(SV P0): SCL-preserved IEC Ed2.1 4I4V smpRate/smpMod wire profiles #285 and Release blocker: eliminate ESP32-P4 START timing misses #92 are zero-behind on CHECKPOINT MERGE: Auto-Live and 5-file capture on PCAP-proven SV/PTP baseline #288 (source preserved).
3. Do not claim total CI pass: recovery Native Preview run 39886625064 had firmware PASS / Windows-preview IN PROGRESS at last observation; standard Draft-routed full test suites remain skipped.
4. Release acceptance: unedited 30s 4kfps + 0 gaps + DigSubAnalyzer/ARSAS + smpSynch acquisition on exactly flashed CHECKPOINT MERGE: Auto-Live and 5-file capture on PCAP-proven SV/PTP baseline #288, then live IA/UA/frequency commits with actual wire readback/continued SV; SIPROTEC 5 PTP LOCKED and 4I4V relay values; STOP/START/soak; packaged Windows lifecycle and full final-head gates. Any failure retains Draft and leaves main untouched.

Net cleanup decision: 25 open PR/21 open issues are real remaining scopes, not 46 interchangeable duplicates. No additional closures justified by ancestry/behavior evidence found this round. Closing unproven items would hide unfinished release risk.

[masarray]

2026-10-23 obsolete PR / issue re-audit — actual GitHub closures

User challenged earlier conclusion that none remained redundant. Re-audited current open candidate against recovered Draft #288 at 90e2755 and the Workbench/SV milestone issue bodies and historical comments.

CLOSED (not merged) PR #279 from original head bc999d3: fully reviewed its three-file compact panel / equal phasor+wave visual allocation / Enter-Tab-focus commit / focus sink patches against #288 replacements. Current narrower panel 405–465px, equal dynamic half-height docks, empty-area forceActiveFocus, and editingFinished-based decimal parser with no 90ms partial SET timer provide semantic successors. Pixel-by-pixel equality / screenshots / physical on-wire AUTO-LIVE acceptance are NOT claimed. Branch retained.
CLOSED duplicate-tracking issue #84 after copying all unique URCB+BRCB root Read, multi-root AccessResult order, GVAA matching type/order, live Owner/reservation state and real third-party IEC 61850 client acceptance checks into OPEN golden-parity #95. Internal Windows CI was PASS historically; external client remains unaccepted.
CLOSED duplicate-tracking issue #33 after copying P3-A0/A1/A2 host SCL/SmvOpts/structured FCDA/profile family/4800 and outstanding binary/device/wire-resolution acceptance into OPEN parent #24 and annotating OPEN children #35 / #36 / #40. Historical main #151 carried binary device-profile transport, but #36/#21 physical 4000/4800 and extra families are NOT accepted. Do not misread tracking closure as conformance.

Actual inventory after re-audit: 24 OPEN PR and 19 OPEN issues, down from 25 PR /21 issues. The remainder were checked for distinct behavior/field requirements; keep the recovery #288 and rejected historical RC #286 DRAFT. Do not merge into main, alter recovery firmware or close external-GM #284, Studio live hardware #253, Windows lifecycle #99, separate Workbench/Simulator PRs without proof. PR #164 and #172 have unique native Workbench code/evidence not present at current main (e.g. MmsSemanticValue.hpp, BrowserEvidenceVisualQa.hpp paths missing at main@7f6b946) and must NOT be swept as 'old'.

Hard release blocker unchanged: #286 042df0d matched package failed real ARSAS/DigSubAnalyzer SV reception, while last healthy 35s/140271 SV ~7s AUTO capture belongs to 7c95f70. #288 source recovery is not itself physical FAT. Requires exact-new-SHA installer+BIN, uninterrupted 30s capture with no GUI edit and both analyzer subscribers, then IA/UA/frequency changes with verified ACK/readback and no PTP/SV restart, SIPROTEC PTP LOCKED+4I4V and full CI. No branch deletion, code edits or merge in this maintenance round.

[masarray]

2026-10-23 rejected historical RC archived · NOT MERGED TO MAIN

Maintainer/operator field gate overrules a green build. The matched Windows+ESP32 firmware package at this draft HEAD 042df0d40ddd3f061ebeebc81c662c585827e346 was physically reported NOT readable as normal SV in ARSAS/DigSubAnalyzer. It was already explicitly WITHDRAWN / RELEASE HOLD in this PR description. Do not let mergeable=true, old full-QML structural tests or Native Preview SUCCESS become a mistaken release approval.

Current replacement, distinct source lineage: PR #288 was MERGED only into dedicated recovery checkpoint checkpoint/sv-ptp-autolive-capture-ci-merged-20261023 (merge commit e82040716c549af887579b369965ba96a890a4db, final reviewed head 8a2428503ee8a1595b03901ac8c1ca2b8343c728), derived from actual 35s PCAP's firmware buildId 7c95f70cced4d126. It is NOT merged into main, nor automatically approved as a public release.

Physical evidence now observed: subsequent 490,881-SV / 375-PTP full-capture analysis of original 7c95 pair showed normal 4000fps within sessions but one 2.359893-second SV gap/START restart, with smpSynch=2→0→2; old GUI UA edited 10→20 V but not applied to wire while manual Apply Live still required. The latest #288 QML AutoLive changes require fresh paired-on-board 10→20 V, IA and frequency no-STOP/no-PTP/smpCnt-reset re-verification; receiver PTP/quality compliance not established, particularly lab SOURCE clockClass/UTC-traceable advertisements inconsistent with diagnostics. Do not misreport a STOP-cycle capture as continuous live-apply proof.

Exact #288 HEAD software CI: ARStack Studio Native Preview #39945242137, Windows Lifecycle #39945241839, standalone ESP32 #39945241867, Qt #39945242093, C++ #39945242034 all SUCCESS. Earlier draft-skipped jobs were subsequently rerun and passed at this source SHA, but software pass ≠ physical acceptance.

Final disposition of THIS old draft #286: close PR UNMERGED / REJECTED RC rather than leave a dangerous obsolete candidate pointing to main. Keep head branch and full discussion untouched for historical patches/rollback. #286 and #288 history DIVERGES: the new recovered checkpoint does not contain every old unverified change; future code recovery must explicitly cherry-pick/retest only necessary behavior. No branch deleted, no code/firmware reverted, no main merge.

Ownership remaining OPEN: #42 live AUTO-LIVE on-wire + reconnect authorization; #154/#162 PTP/SV/smpSynch & IED lock; #99 lifecycle historical source review; #289 spec-only always-on PTP/SV; #253 previous live transaction/reconnect safety semantics; dedicated future new Stage→Main PR only after accepted #288-based physical evidence and explicit release decision.