Convert registers to RDL, remove templating, convert to APB

[micprog]

Changed

• Converts registers to SystemRDL generated by peakrdl
• Integration flow of clint.mk
• switched from lowRISC license checker to REUSE
• Renamed test bender target to tb which currently only holds the clint testbench

Added

• adapts a pyproject.toml for python dependencies i.e. peakrdl managed by uv
• tracks Bender.lock file now for reproducability

Removed

• pip managed requirements.txt

CI

• switched from lowRISC license checker to REUSE
• bumped all github actions to the newest versions

[Lore0599]

Thanks a lot for your contribution, overall, LGTM!
I left some minor comments, mostly related to naming conventions that differ from the official SystemRDL style.
We could agree on a common structure for naming internal sub-fields. In particular, as highlighted in the SystemRDL style guide, I would recommend avoiding excessive prefixes, which can be overly verbose. Since the generated top-level register file follows a structured approach, the regfile name is already visible when accessing internal sub-fields, making such prefixes unnecessary.

[fischeti]

I took the liberty to push some commits to this PR that also address @Lore0599 suggestions🤓

The hierarchical names should now be as minimal as possible without redundant prefixes.

I also renamed clint_reg_top to clint_reg and updated the clint.mk make fragment.

[paulsc96]

Looks solid overall. But I have no prior experience with SystemRDL, so I can't really vouch for the new generation approach.

It's a bit unfortunate that we are still stuck with generation to begin with, but SystemRDL/PeakRDL#54 / SystemRDL/PeakRDL-regblock#33 / SystemRDL/systemrdl-compiler#58 don't seem like they will make any progress this millenium, so we might aswell move now.

I won't be around much longer, so if anyone wants to take over maintainership of this repo, go right ahead.

[fischeti]

Yes, parametrizable register block output would be amazing. But it's already an improvement to what we had before

[ezelioli]

I don't have previous experience with SystemRDL, but I like the idea of moving away from reggen and to use a standard bus like APB. Following the previous discussion I guess there is no way (yet) to make the number of cores a parameter of the generated sv, which would be an obvious improvement. Is this correct?
In any case, LGTM :)

[fischeti]

That is correct. It is not yet possible to expose this as a parameter to the generated SV regblock unfortunately.