Updates on Linting: tc_sram, SIM_STDOUT=0. Connect testmode_i in axi_scmi_mailbox.

.gitlab-ci.yml

@@ -73,8 +73,8 @@ spyglass:
   stage: lint
   script:
     - make cp-sg-lint
-    - (! grep -n "Fatal" util/lint/spyglass/sg_projects/pms/pms_top/Design_Read/spyglass_reports/moresimple.rpt)
-    - (! grep -n "Fatal" util/lint/spyglass/sg_projects/pms/pms_top/lint/lint_rtl/spyglass_reports/moresimple.rpt)
+    - (! grep -n "FATAL" util/lint/spyglass/sg_projects/pms/pms_top/Design_Read/spyglass_reports/moresimple.rpt)
+    - (! grep -n "FATAL" util/lint/spyglass/sg_projects/pms/pms_top/lint/lint_rtl/spyglass_reports/moresimple.rpt)
 
   artifacts:
     name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"

.gitmodules

@@ -96,7 +96,7 @@
 	url = https://github.com/pulp-platform/scm.git
 [submodule "hw/ips/tech_cells_generic"]
 	path = hw/ips/tech_cells_generic
-	url = https://github.com/pulp-platform/tech_cells_generic.git
+	url = git@github.com:pulp-platform/tech_cells_generic.git
 [submodule "hw/ips/timer_unit"]
 	path = hw/ips/timer_unit
 	url = https://github.com/pulp-platform/timer_unit.git

Bender.yml

@@ -26,6 +26,7 @@ package:
     - "Gianmarco Ottavi <gianmarco.ottavi@studio.unibo.it>"
     - "Manuel Eggimann <meggiman@iis.ee.ethz.ch>"
     - "Luca Valente <luca.valente2@unibo.it>"
+    - "Simone Manoni <s.manoni@unibo.it>"
 
 dependencies:
   control_pulp_pkg: { path: "hw/pkg" }
@@ -71,21 +72,6 @@ sources:
   - hw/pulp/control_pulp.sv
   - hw/pulp/control_pulp_fpga.sv
 
-  - target: all(lint_pms)
-    files:
-      - hw/ips/tech_cells_generic/src/rtl/tc_sram.sv
-      - hw/ips/tech_cells_generic/src/rtl/tc_sram_impl.sv
-      - hw/ips/tech_cells_generic/src/rtl/tc_clk.sv
-      - hw/ips/tech_cells_generic/src/deprecated/cluster_pwr_cells.sv
-      - hw/ips/tech_cells_generic/src/deprecated/generic_memory.sv
-      - hw/ips/tech_cells_generic/src/deprecated/generic_rom.sv
-      - hw/ips/tech_cells_generic/src/deprecated/pad_functional.sv
-      - hw/ips/tech_cells_generic/src/deprecated/pulp_buffer.sv
-      - hw/ips/tech_cells_generic/src/deprecated/pulp_pwr_cells.sv
-      - hw/ips/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv
-      - hw/ips/tech_cells_generic/src/deprecated/cluster_clk_cells.sv
-      - hw/ips/tech_cells_generic/src/deprecated/pulp_clk_cells.sv
-
   # TB sources
   - target: any(test,simulation)
     files:
@@ -148,7 +134,7 @@ sources:
       - tb/vip/i2c_eeprom/24FC1025.v
 
   # tech (gf22)
-  - target: all(gf22, not(lint_pms))
+  - target: all(gf22)
     files:
       - nonfree/synth/gf22/sourcecode/tech_cells_gf22/pulp_power_gating.sv
       - nonfree/synth/gf22/sourcecode/tech_cells_gf22/cluster_clock_inverter.sv

hw/ips/axi_scmi_mailbox/rtl/axi_scmi_mailbox.sv

@@ -32,6 +32,8 @@ module axi_scmi_mailbox
   input  logic       clk_i, // Clock
   input  logic       rst_ni, // Asynchronous reset active low
 
+  input  logic       testmode_i, // Test mode (for scan)
+
   input  axi_req_t   axi_mbox_req,
   output axi_resp_t  axi_mbox_rsp,
 
@@ -258,7 +260,7 @@ module axi_scmi_mailbox
    ) u_axi2reg_intf (
      .clk_i,
      .rst_ni,
-     .testmode_i(1'b0),
+     .testmode_i(testmode_i),
      .axi_req_i(axi32_mbox_req),
      .axi_rsp_o(axi32_mbox_rsp),
      .reg_req_o(reg_req),

hw/pulp/control_pulp_fpga.sv

@@ -635,7 +635,7 @@ module control_pulp_fpga import pms_top_pkg::*; #(
     .rst_ni          (rst_ni         ),
     .axi_mbox_req    (to_mailbox_req ),
     .axi_mbox_rsp    (to_mailbox_resp),
-
+    .testmode_i      (1'b0            ),
     .irq_completion_o    (/*TODO*/),  // completion irq platform->agent
     .irq_doorbell_o      ({mbox_irq, scp_secure_irq, scp_irq, scg_irq})  // doorbell irq agent->platform
   );

hw/pulp/pms_top.sv

@@ -29,7 +29,7 @@ module pms_top import pms_top_pkg::*; #(
   parameter int unsigned  CORE_TYPE = 0, // 0 for CV32E40P (other options are not supported)
   parameter int unsigned  USE_FPU = 1,
   parameter int unsigned  PULP_XPULP = 1,
-  parameter int unsigned  SIM_STDOUT = 1,
+  parameter int unsigned  SIM_STDOUT = 0,
   parameter int unsigned  BEHAV_MEM = 1,
   parameter int unsigned  MACRO_ROM = 0,
   parameter int unsigned  USE_CLUSTER = 1,

util/lint/spyglass/run_sg_lint.tcl

@@ -11,11 +11,6 @@ set TIMESTAMP [exec date +%Y%m%d_%H%M%S]
 new_project sg_projects/${PROJECT}_${TIMESTAMP}
 current_methodology $env(SPYGLASS_HOME)/GuideWare/latest/block/rtl_handoff
 
-# Ignore re-defined files
-#foreach file $IgnoredFiles {
-#  set_option ignorefile $file
-#}
-
 # Read the RTL
 read_file -type sourcelist cp_sg.f
 
@@ -29,6 +24,9 @@ set_option designread_disable_flatten no
 set_option mthresh 32768
 set_option top pms_top
 
+# Waive empty module warnings
+waive -rule "WarnAnalyzeBBox"
+
 # Link Design
 current_design pms_top
 compile_design