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Add support for SPM in the HPDCache subsystem #69

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2dc019d
hpdcache_subsystem: add SPM mode support
ricted98 Apr 10, 2026
91dcefc
hpdcache_tc_sram: fix missing parameter
ricted98 Apr 10, 2026
031e0a6
csr_regfile: check `v_q` only when `RVH` is enabled
ricted98 Apr 10, 2026
2d31dd5
hpdcache: fixes for ISPM support
ricted98 Apr 13, 2026
9626cf7
tests: use `fence.i` for DSPM tests to ensure cache flushing
ricted98 Apr 13, 2026
450aa19
core: fix verible formatting
ricted98 Apr 13, 2026
375c5d1
test: adopt `cv64a6_imafdchsclic_sv39_hpdcache_wb` as baseline config…
ricted98 Apr 13, 2026
c8d66b5
hpdcache: bump submodule
ricted98 Apr 22, 2026
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52 changes: 49 additions & 3 deletions core/cache_subsystem/cva6_hpdcache_if_adapter.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,8 @@ module cva6_hpdcache_if_adapter
} flush_fsm_t;

logic hpdcache_req_is_uncacheable;
logic hpdcache_req_is_ispm;
logic hpdcache_req_is_dspm;
hpdcache_req_t hpdcache_req;
// }}}

Expand All @@ -85,6 +87,22 @@ module cva6_hpdcache_if_adapter
, cva6_req_i.address_tag
, {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}
}
) && !hpdcache_req_is_ispm && !hpdcache_req_is_dspm;
assign hpdcache_req_is_ispm = config_pkg::is_inside_ispm_regions(
CVA6Cfg,
{
{64 - CVA6Cfg.DCACHE_TAG_WIDTH{1'b0}}
, cva6_req_i.address_tag
, {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}
}
);
assign hpdcache_req_is_dspm = config_pkg::is_inside_dspm_regions(
CVA6Cfg,
{
{64 - CVA6Cfg.DCACHE_TAG_WIDTH{1'b0}}
, cva6_req_i.address_tag
, {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}
}
);

// Request forwarding
Expand All @@ -102,12 +120,16 @@ module cva6_hpdcache_if_adapter
assign hpdcache_req.pma.uncacheable = 1'b0;
assign hpdcache_req.pma.io = 1'b0;
assign hpdcache_req.pma.wr_policy_hint = hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO;
assign hpdcache_req.pma.ispm = 1'b0;
assign hpdcache_req.pma.dspm = 1'b0;

assign hpdcache_req_abort_o = cva6_req_i.kill_req;
assign hpdcache_req_tag_o = cva6_req_i.address_tag;
assign hpdcache_req_pma_o.uncacheable = hpdcache_req_is_uncacheable;
assign hpdcache_req_pma_o.io = 1'b0;
assign hpdcache_req_pma_o.wr_policy_hint = hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO;
assign hpdcache_req_pma_o.ispm = hpdcache_req_is_ispm;
assign hpdcache_req_pma_o.dspm = hpdcache_req_is_dspm;

// Response forwarding
assign cva6_req_o.data_rvalid = hpdcache_rsp_valid_i;
Expand Down Expand Up @@ -235,6 +257,22 @@ module cva6_hpdcache_if_adapter
, hpdcache_req.addr_tag,
{CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}
}
) && !hpdcache_req_is_ispm && !hpdcache_req_is_dspm;
assign hpdcache_req_is_ispm = config_pkg::is_inside_ispm_regions(
CVA6Cfg,
{
{64 - CVA6Cfg.DCACHE_TAG_WIDTH{1'b0}}
, cva6_req_i.address_tag
, {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}
}
);
assign hpdcache_req_is_dspm = config_pkg::is_inside_dspm_regions(
CVA6Cfg,
{
{64 - CVA6Cfg.DCACHE_TAG_WIDTH{1'b0}}
, cva6_req_i.address_tag
, {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}
}
);

assign amo_is_word = (cva6_amo_req_i.size == 2'b10);
Expand All @@ -261,7 +299,9 @@ module cva6_hpdcache_if_adapter
pma: '{
uncacheable: hpdcache_req_is_uncacheable,
io: 1'b0,
wr_policy_hint: hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO
wr_policy_hint: hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO,
ispm: 1'b0, // TODO: SPM AMOs support
dspm: 1'b0 // TODO: SPM AMOs support
}
};

Expand All @@ -282,7 +322,9 @@ module cva6_hpdcache_if_adapter
pma: '{
uncacheable: hpdcache_req_is_uncacheable,
io: 1'b0,
wr_policy_hint: hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO
wr_policy_hint: hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO,
ispm: hpdcache_req_is_ispm,
dspm: hpdcache_req_is_dspm
}
};

Expand All @@ -305,7 +347,9 @@ module cva6_hpdcache_if_adapter
pma: '{
uncacheable: 1'b0,
io: 1'b0,
wr_policy_hint: hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO
wr_policy_hint: hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO,
ispm: 1'b0,
dspm: 1'b0
}
};

Expand All @@ -322,6 +366,8 @@ module cva6_hpdcache_if_adapter
assign hpdcache_req_pma_o.uncacheable = 1'b0;
assign hpdcache_req_pma_o.io = 1'b0;
assign hpdcache_req_pma_o.wr_policy_hint = hpdcache_pkg::HPDCACHE_WR_POLICY_AUTO;
assign hpdcache_req_pma_o.ispm = 1'b0;
assign hpdcache_req_pma_o.dspm = 1'b0;
// }}}

// Response forwarding
Expand Down
23 changes: 18 additions & 5 deletions core/cache_subsystem/cva6_hpdcache_subsystem.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,8 @@ module cva6_hpdcache_subsystem
input logic icache_flush_i,
// instruction cache miss - PERF_COUNTERS
output logic icache_miss_o,
// I-cache ways configured as SPM - CSR_REGFILE
input logic [CVA6Cfg.ICACHE_SET_ASSOC-1:0] icache_spm_ways_i,
// Input address translation request - EX_STAGE
input icache_areq_t icache_areq_i,
// Output address translation request - EX_STAGE
Expand All @@ -79,13 +81,15 @@ module cva6_hpdcache_subsystem
// {{{
// Cache management
// Data cache enable - CSR_REGFILE
input logic dcache_enable_i,
input logic dcache_enable_i,
// Data cache flush - CONTROLLER
input logic dcache_flush_i,
input logic dcache_flush_i,
// Flush acknowledge - CONTROLLER
output logic dcache_flush_ack_o,
// Load or store miss - PERF_COUNTERS
output logic dcache_miss_o,
// D-cache ways configured as SPM - CSR_REGFILE
input logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] dcache_spm_ways_i,

// AMO request - EX_STAGE
input ariane_pkg::amo_req_t dcache_amo_req_i,
Expand Down Expand Up @@ -145,6 +149,10 @@ module cva6_hpdcache_subsystem
logic icache_miss_resp_valid;
icache_rtrn_t icache_miss_resp;

// D-cache <-> I-cache SPM signals
dcache_req_o_t d2i_cache_req_in;
dcache_req_i_t d2i_cache_req_out;

localparam int ICACHE_RDTXID = 1 << (CVA6Cfg.MEM_TID_WIDTH - 1);

cva6_icache #(
Expand All @@ -155,6 +163,8 @@ module cva6_hpdcache_subsystem
.icache_drsp_t(icache_drsp_t),
.icache_req_t(icache_req_t),
.icache_rtrn_t(icache_rtrn_t),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.RdTxId(ICACHE_RDTXID)
) i_cva6_icache (
.clk_i (clk_i),
Expand All @@ -165,13 +175,13 @@ module cva6_hpdcache_subsystem
.busy_o (),
.stall_i (1'b0),
.init_ni (1'b0),
.icache_spm_ways_i('0),
.icache_spm_ways_i(icache_spm_ways_i),
.areq_i (icache_areq_i),
.areq_o (icache_areq_o),
.dreq_i (icache_dreq_i),
.dreq_o (icache_dreq_o),
.ispm_req_i ('0),
.ispm_req_o (),
.ispm_req_i (d2i_cache_req_out),
.ispm_req_o (d2i_cache_req_in),
.mem_rtrn_vld_i (icache_miss_resp_valid),
.mem_rtrn_i (icache_miss_resp),
.mem_data_req_o (icache_miss_valid),
Expand Down Expand Up @@ -329,6 +339,9 @@ module cva6_hpdcache_subsystem
.dcache_req_ports_o(dcache_req_ports_o),
.wbuffer_empty_o(wbuffer_empty_o),
.wbuffer_not_ni_o(wbuffer_not_ni_o),
.dcache_spm_ways_i(dcache_spm_ways_i),
.ispm_req_o(d2i_cache_req_out),
.ispm_req_i(d2i_cache_req_in),
.hwpf_base_set_i(hwpf_base_set_i),
.hwpf_base_i(hwpf_base_i),
.hwpf_base_o(hwpf_base_o),
Expand Down
82 changes: 70 additions & 12 deletions core/cache_subsystem/cva6_hpdcache_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -81,6 +81,13 @@ module cva6_hpdcache_wrapper
output logic wbuffer_empty_o,
output logic wbuffer_not_ni_o,

// SPM ways configuration
input logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] dcache_spm_ways_i,

// ISPM interface (request to i-cache scratchpad / response from i-cache scratchpad)
output dcache_req_i_t ispm_req_o,
input dcache_req_o_t ispm_req_i,

// Hardware memory prefetcher configuration
input logic [NrHwPrefetchers-1:0] hwpf_base_set_i,
input logic [NrHwPrefetchers-1:0][63:0] hwpf_base_i,
Expand Down Expand Up @@ -128,6 +135,38 @@ module cva6_hpdcache_wrapper
hpdcache_rsp_t dcache_rsp [HPDCACHE_NREQUESTERS];
logic dcache_read_miss, dcache_write_miss;

// ISPM internal signals
logic dcache_ispm_req_valid;
hpdcache_req_t dcache_ispm_req;
logic dcache_ispm_req_abort;
hpdcache_tag_t dcache_ispm_req_tag;
hpdcache_pkg::hpdcache_pma_t dcache_ispm_req_pma;
logic dcache_ispm_rsp_valid;
hpdcache_rsp_t dcache_ispm_rsp;

// ISPM request conversion: hpdcache -> i-cache ISPM controller
assign ispm_req_o.data_req = dcache_ispm_req_valid;
assign ispm_req_o.address_index = dcache_ispm_req.addr_offset;
assign ispm_req_o.address_tag = dcache_ispm_req_tag;
assign ispm_req_o.data_wdata = dcache_ispm_req.wdata;
assign ispm_req_o.data_wuser = '0;
assign ispm_req_o.data_we = (dcache_ispm_req.op != hpdcache_pkg::HPDCACHE_REQ_LOAD);
assign ispm_req_o.data_be = dcache_ispm_req.be;
assign ispm_req_o.data_size = dcache_ispm_req.size;
assign ispm_req_o.data_id = dcache_ispm_req.tid;
assign ispm_req_o.kill_req = dcache_ispm_req_abort;
assign ispm_req_o.tag_valid = dcache_ispm_req_valid;
assign ispm_req_o.cbo_op = '0;

// ISPM response conversion: i-cache ISPM controller -> hpdcache
// sid/tid are echoed from the still-valid outgoing request
assign dcache_ispm_rsp_valid = ispm_req_i.data_rvalid || ispm_req_i.data_gnt; // TODO: is this correct?
assign dcache_ispm_rsp.rdata = ispm_req_i.data_rdata;
assign dcache_ispm_rsp.sid = dcache_ispm_req.sid;
assign dcache_ispm_rsp.tid = dcache_ispm_req.tid;
assign dcache_ispm_rsp.error = 1'b0;
assign dcache_ispm_rsp.aborted = 1'b0;

logic [ 2:0] snoop_valid;
logic [ 2:0] snoop_abort;
hpdcache_req_offset_t [ 2:0] snoop_addr_offset;
Expand Down Expand Up @@ -398,17 +437,30 @@ module cva6_hpdcache_wrapper
.mem_resp_write_valid_i(dcache_mem_resp_write_valid_i),
.mem_resp_write_i (dcache_mem_resp_write_i),

.evt_cache_write_miss_o(dcache_write_miss),
.evt_cache_read_miss_o (dcache_read_miss),
.evt_uncached_req_o ( /* unused */),
.evt_cmo_req_o ( /* unused */),
.evt_write_req_o ( /* unused */),
.evt_read_req_o ( /* unused */),
.evt_prefetch_req_o ( /* unused */),
.evt_req_on_hold_o ( /* unused */),
.evt_rtab_rollback_o ( /* unused */),
.evt_stall_refill_o ( /* unused */),
.evt_stall_o ( /* unused */),
.ispm_req_valid_o(dcache_ispm_req_valid),
.ispm_req_o (dcache_ispm_req),
.ispm_req_abort_o(dcache_ispm_req_abort),
.ispm_req_tag_o (dcache_ispm_req_tag),
.ispm_req_pma_o (dcache_ispm_req_pma),
.ispm_rsp_valid_i(dcache_ispm_rsp_valid),
.ispm_rsp_i (dcache_ispm_rsp),

.evt_cache_write_miss_o (dcache_write_miss),
.evt_cache_read_miss_o (dcache_read_miss),
.evt_cache_dir_unc_err_o( /* unused */),
.evt_cache_dir_cor_err_o( /* unused */),
.evt_cache_dat_unc_err_o( /* unused */),
.evt_cache_dat_cor_err_o( /* unused */),
.evt_scrub_complete_o ( /* unused */),
.evt_uncached_req_o ( /* unused */),
.evt_cmo_req_o ( /* unused */),
.evt_write_req_o ( /* unused */),
.evt_read_req_o ( /* unused */),
.evt_prefetch_req_o ( /* unused */),
.evt_req_on_hold_o ( /* unused */),
.evt_rtab_rollback_o ( /* unused */),
.evt_stall_refill_o ( /* unused */),
.evt_stall_o ( /* unused */),

.wbuf_empty_o(wbuffer_empty_o),

Expand All @@ -420,7 +472,13 @@ module cva6_hpdcache_wrapper
.cfg_prefetch_updt_plru_i (1'b1),
.cfg_error_on_cacheable_amo_i (1'b0),
.cfg_rtab_single_entry_i (1'b0),
.cfg_default_wb_i (1'b0)
.cfg_default_wb_i (1'b0),
.cfg_scrub_enable_i (1'b0),
.cfg_scrub_period_i (6'd0),
.cfg_scrub_restart_i (1'b0),
.cfg_enable_dspm_i (1'b1),
.cfg_enable_ispm_i (1'b1),
.cfg_dspm_ways_i (dcache_spm_ways_i)
);

assign dcache_miss_o = dcache_read_miss, wbuffer_not_ni_o = wbuffer_empty_o;
Expand Down
2 changes: 1 addition & 1 deletion core/cache_subsystem/hpdcache
Open in desktop
Submodule hpdcache updated 84 files
+15 −32 .github/actions/run_sequence/action.yml
+32 −0 .github/workflows/test.yml
+28 −0 CHANGELOG.md
+65 −0 CONTRIBUTING.md
+2 −16 LICENSE
+52 −19 README.md
+1 −1 docs/source/overview.rst
+3 −0 py-requirements.txt
+2 −16 rtl/hpdcache.Flist
+2 −15 rtl/include/hpdcache_typedef.svh
+7 −0 rtl/lint/Makefile
+30 −30 rtl/lint/hpdcache_lint.sv
+58 −37 rtl/src/common/hpdcache_sram.sv
+63 −39 rtl/src/common/hpdcache_sram_wbyteenable.sv
+64 −39 rtl/src/common/hpdcache_sram_wmask.sv
+36 −26 rtl/src/common/macros/behav/hpdcache_sram_1rw.sv
+90 −0 rtl/src/common/macros/behav/hpdcache_sram_ecc_1rw.sv
+42 −30 rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_1rw.sv
+126 −0 rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_ecc_1rw.sv
+37 −27 rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv
+105 −0 rtl/src/common/macros/behav/hpdcache_sram_wmask_ecc_1rw.sv
+12 −23 rtl/src/common/macros/blackbox/hpdcache_sram_1rw.sv
+36 −0 rtl/src/common/macros/blackbox/hpdcache_sram_ecc_1rw.sv
+13 −24 rtl/src/common/macros/blackbox/hpdcache_sram_wbyteenable_1rw.sv
+37 −0 rtl/src/common/macros/blackbox/hpdcache_sram_wbyteenable_ecc_1rw.sv
+13 −24 rtl/src/common/macros/blackbox/hpdcache_sram_wmask_1rw.sv
+37 −0 rtl/src/common/macros/blackbox/hpdcache_sram_wmask_ecc_1rw.sv
+57 −20 rtl/src/hpdcache.sv
+742 −205 rtl/src/hpdcache_ctrl.sv
+260 −58 rtl/src/hpdcache_ctrl_pe.sv
+253 −94 rtl/src/hpdcache_memctrl.sv
+17 −6 rtl/src/hpdcache_mshr.sv
+10 −17 rtl/src/hpdcache_pkg.sv
+145 −0 rtl/src/hpdcache_plru.sv
+20 −33 rtl/src/hpdcache_rtab.sv
+30 −19 rtl/src/hpdcache_uncached.sv
+8 −5 rtl/src/hpdcache_victim_plru.sv
+7 −4 rtl/src/hpdcache_victim_random.sv
+8 −1 rtl/src/hpdcache_victim_sel.sv
+59 −0 rtl/src/utils/ecc/prim_secded_36_29_dec.sv
+23 −0 rtl/src/utils/ecc/prim_secded_36_29_enc.sv
+62 −0 rtl/src/utils/ecc/prim_secded_39_32_dec.sv
+23 −0 rtl/src/utils/ecc/prim_secded_39_32_enc.sv
+78 −0 rtl/src/utils/ecc/prim_secded_55_48_dec.sv
+23 −0 rtl/src/utils/ecc/prim_secded_55_48_enc.sv
+95 −0 rtl/src/utils/ecc/prim_secded_72_64_dec.sv
+24 −0 rtl/src/utils/ecc/prim_secded_72_64_enc.sv
+81 −0 rtl/src/utils/ecc/prim_secded_inc.svh
+466 −0 rtl/src/utils/ecc/prim_secded_pkg.sv
+15 −2 rtl/syn/hpdcache_wrapper.sv
+11 −9 rtl/syn/srams/fakeram45/hpdcache_sram_fakeram45_1rw.sv
+17 −13 rtl/syn/srams/fakeram45/hpdcache_sram_wbyteenable_fakeram45_1rw.sv
+15 −14 rtl/syn/srams/fakeram45/hpdcache_sram_wmask_fakeram45_1rw.sv
+54 −54 rtl/tb/Makefile
+36 −1 rtl/tb/README.md
+4 −16 rtl/tb/configs/default_config.mk
+3 −1 rtl/tb/configs/directmap_config.mk
+4 −16 rtl/tb/configs/embedded_config.mk
+5 −17 rtl/tb/configs/hpc_config.mk
+19 −15 rtl/tb/hpdcache.vlt.Flist
+30 −15 rtl/tb/hpdcache_tb.cpp
+52 −20 rtl/tb/hpdcache_wrapper.sv
+192 −0 rtl/tb/include/hpdcache_fault_injection.h
+5 −0 rtl/tb/include/hpdcache_test_agent.h
+3 −16 rtl/tb/include/hpdcache_test_defs.h
+28 −17 rtl/tb/include/hpdcache_test_driver.h
+40 −15 rtl/tb/include/hpdcache_test_scoreboard.h
+58 −19 rtl/tb/include/hpdcache_test_transaction.h
+6 −0 rtl/tb/rtl_conf.mk
+24 −0 rtl/tb/scripts/check_format_tb.sh
+100 −0 rtl/tb/scripts/run_nonregression.sh
+61 −0 rtl/tb/scripts/smoke_tests.sh
+64 −25 rtl/tb/sequence_lib/hpdcache_test_random_seq.h
+14 −0 vendor/lowrisc_opentitan.lock.hjson
+29 −0 vendor/lowrisc_opentitan.vendor.hjson
+17 −0 vendor/opentitan/util/basegen/BUILD
+3 −0 vendor/opentitan/util/basegen/__init__.py
+93 −0 vendor/opentitan/util/basegen/lib.py
+13 −0 vendor/opentitan/util/basegen/typing.py
+27 −0 vendor/opentitan/util/design/data/secded_cfg.hjson
+1,160 −0 vendor/opentitan/util/design/secded_gen.py
+68 −0 vendor/patches/opentitan/util/design/001_secded_gen_no_c.patch
+4 −0 vendor/update_vendor.sh
+803 −0 vendor/vendor.py
63 changes: 33 additions & 30 deletions core/cache_subsystem/hpdcache_tc_sram.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,20 +10,21 @@
module hpdcache_sram_1rw #(
parameter int unsigned ADDR_SIZE = 0,
parameter int unsigned DATA_SIZE = 0,
parameter int unsigned DEPTH = 2 ** ADDR_SIZE
parameter int unsigned DEPTH = 2 ** ADDR_SIZE,
parameter int unsigned NDATA = 1
) (
input logic clk,
input logic rst_n,
input logic cs,
input logic we,
input logic [ADDR_SIZE-1:0] addr,
input logic [DATA_SIZE-1:0] wdata,
output logic [DATA_SIZE-1:0] rdata
input logic clk,
input logic rst_n,
input logic cs,
input logic we,
input logic [ADDR_SIZE-1:0] addr,
input logic [ NDATA-1:0][DATA_SIZE-1:0] wdata,
output logic [ NDATA-1:0][DATA_SIZE-1:0] rdata
);
tc_sram #(
.NumWords (DEPTH),
.DataWidth(DATA_SIZE),
.ByteWidth(DATA_SIZE),
.DataWidth(DATA_SIZE * NDATA),
.ByteWidth(DATA_SIZE * NDATA),
.NumPorts (1),
.Latency (1)
) i_tc_sram (
Expand All @@ -42,20 +43,21 @@ endmodule
module hpdcache_sram_wbyteenable_1rw #(
parameter int unsigned ADDR_SIZE = 0,
parameter int unsigned DATA_SIZE = 0,
parameter int unsigned DEPTH = 2 ** ADDR_SIZE
parameter int unsigned DEPTH = 2 ** ADDR_SIZE,
parameter int unsigned NDATA = 1
) (
input logic clk,
input logic rst_n,
input logic cs,
input logic we,
input logic [ ADDR_SIZE-1:0] addr,
input logic [ DATA_SIZE-1:0] wdata,
input logic [DATA_SIZE/8-1:0] wbyteenable,
output logic [ DATA_SIZE-1:0] rdata
input logic clk,
input logic rst_n,
input logic cs,
input logic we,
input logic [ADDR_SIZE-1:0] addr,
input logic [ NDATA-1:0][ DATA_SIZE-1:0] wdata,
input logic [ NDATA-1:0][DATA_SIZE/8-1:0] wbyteenable,
output logic [ NDATA-1:0][ DATA_SIZE-1:0] rdata
);
tc_sram #(
.NumWords (DEPTH),
.DataWidth(DATA_SIZE),
.DataWidth(DATA_SIZE * NDATA),
.ByteWidth(8),
.NumPorts (1),
.Latency (1)
Expand All @@ -75,20 +77,21 @@ endmodule
module hpdcache_sram_wmask_1rw #(
parameter int unsigned ADDR_SIZE = 0,
parameter int unsigned DATA_SIZE = 0,
parameter int unsigned DEPTH = 2 ** ADDR_SIZE
parameter int unsigned DEPTH = 2 ** ADDR_SIZE,
parameter int unsigned NDATA = 1
) (
input logic clk,
input logic rst_n,
input logic cs,
input logic we,
input logic [ADDR_SIZE-1:0] addr,
input logic [DATA_SIZE-1:0] wdata,
input logic [DATA_SIZE-1:0] wmask,
output logic [DATA_SIZE-1:0] rdata
input logic clk,
input logic rst_n,
input logic cs,
input logic we,
input logic [ADDR_SIZE-1:0] addr,
input logic [ NDATA-1:0][DATA_SIZE-1:0] wdata,
input logic [ NDATA-1:0][DATA_SIZE-1:0] wmask,
output logic [ NDATA-1:0][DATA_SIZE-1:0] rdata
);
tc_sram #(
.NumWords (DEPTH),
.DataWidth(DATA_SIZE),
.DataWidth(DATA_SIZE * NDATA),
.ByteWidth(1),
.NumPorts (1),
.Latency (1)
Expand Down
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