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tree-sitter-verilog: add build-tree-sitter-verilog.yml for riscv64 wheels - #1196

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luhenry merged 1 commit into
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tree-sitter-verilog
Sep 7, 2026
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tree-sitter-verilog: add build-tree-sitter-verilog.yml for riscv64 wheels#1196
luhenry merged 1 commit into
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tree-sitter-verilog

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@luhenry luhenry commented Sep 6, 2026

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Compiles the Verilog tree-sitter grammar into a cp39-abi3 wheel. Upstream publishes no riscv64 wheel.

Mirrors upstream's package-pypi.yml.

Differs from upstream

  • Nothing beyond the riscv64 image.

Testing

  • same as upstream

License: OK

Built on cp312; 1 passed, 0 skipped.

…eels

Mirrors upstream's package-pypi.yml wheel builder, narrowed to riscv64.
Same shape as the tree-sitter-json/-toml ports already in this repo:
src/parser.c is committed at the release tag, so no generate step is
needed.
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luhenry merged commit b06b9b8 into main Sep 7, 2026
8 of 9 checks passed
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luhenry deleted the tree-sitter-verilog branch September 7, 2026 08:22
@luhenry luhenry linked an issue Sep 7, 2026 that may be closed by this pull request
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tree-sitter-verilog riscv64 support

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