Add support for hierarchical module instantiation syntax

[robtaylor]

Summary

This PR adds parsing and HIR support for Verilog-A hierarchical module instantiation syntax:

module_name #(.param(value)) instance_name (port1, port2);

This syntax is used in some foundry PDK models (e.g., GlobalFoundries GF130 ESD models) to instantiate primitive modules like resistors and capacitors with parameter overrides.

Example from GF130 ESD model:

resistor #(.r(rwire)) r1 (d, de0);
resistor #(.r(rdummy)) r4 (de0, de1);

Changes

• Add ModuleInst grammar to veriloga.ungram with ParamAssignments and PortConnections
• Implement parser grammar with lookahead to distinguish module instantiation from net declarations
• Add ModuleInstItem HIR type to store instance name, module type, parameter assignments, and port connections
• Add HIR lowering for module instances
• Module instances are recorded but don't participate in name resolution (they will be processed during elaboration/flattening)
• Add unit tests for item_tree and def_map
• Add integration test with sample VA file

Limitations

This is parsing support only. The actual instantiation/flattening of modules is not implemented - the instances are simply stored in the HIR for potential future use. This allows models using module instantiation to compile (the instances are ignored during code generation).

Test plan

• New unit tests for item_tree and def_map pass
• Existing tests continue to pass
• GF130 ESD models that previously failed now compile successfully

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