Skip to content

Add built-in primitive module support (resistor, capacitor, inductor)#14

Open
robtaylor wants to merge 6 commits into
allow-analog-in-conditionalsfrom
builtin-primitive-support
Open

Add built-in primitive module support (resistor, capacitor, inductor)#14
robtaylor wants to merge 6 commits into
allow-analog-in-conditionalsfrom
builtin-primitive-support

Conversation

@robtaylor

@robtaylor robtaylor commented Dec 2, 2025

Copy link
Copy Markdown
Owner

Summary

  • Add support for built-in primitive modules (resistor, capacitor, inductor) that transform into equivalent contribution statements during HIR body lowering
  • Fix crash when compiling models with BoundStep outputs

Built-in Primitive Transformations

Primitive Verilog-A Equivalent Contribution
resistor #(.r(R)) r1 (a, b) → I(a,b) <+ V(a,b) / R
capacitor #(.c(C)) c1 (a, b) → I(a,b) <+ ddt(C * V(a,b))
inductor #(.l(L)) l1 (a, b) → V(a,b) <+ ddt(L * I(a,b))

This enables PDK models (like GF130) that use built-in primitives to compile successfully without defining the primitive modules explicitly.

Changes

  • Add BuiltInPrimitive enum in builtin.rs
  • Store parameter expressions as AstPtr in ModuleInstItem (changed from Name)
  • Implement lower_primitive_instances() in body/lower.rs to generate synthetic contribution statements
  • Add test case for primitive module lowering

Test plan

  • All hir_def tests pass
  • New primitive_modules.va test verifies correct lowering output
  • Test with GF130 PDK models that use primitives

🤖 Generated with Claude Code

@robtaylor
robtaylor force-pushed the builtin-primitive-support branch 2 times, most recently from 268b07e to bcc7756 Compare December 18, 2025 13:16
@robtaylor
robtaylor force-pushed the module-instantiation-support branch from ca84621 to 6bdf113 Compare December 18, 2025 14:33
@robtaylor
robtaylor force-pushed the builtin-primitive-support branch from bcc7756 to d5889ea Compare December 18, 2025 14:33
@robtaylor
robtaylor changed the base branch from module-instantiation-support to allow-analog-in-conditionals December 18, 2025 14:34
@robtaylor
robtaylor force-pushed the allow-analog-in-conditionals branch 5 times, most recently from c7ae814 to 882ca3a Compare December 18, 2025 18:03
@robtaylor
robtaylor force-pushed the builtin-primitive-support branch 2 times, most recently from 00f9083 to 2a714c8 Compare December 18, 2025 18:11
@robtaylor
robtaylor force-pushed the allow-analog-in-conditionals branch from 882ca3a to 449993c Compare December 18, 2025 18:23
@robtaylor
robtaylor force-pushed the builtin-primitive-support branch 4 times, most recently from 427fe7e to 2e32d2c Compare December 18, 2025 18:46
@robtaylor
robtaylor force-pushed the allow-analog-in-conditionals branch from 449993c to 1f90eea Compare December 23, 2025 00:26
@robtaylor
robtaylor force-pushed the builtin-primitive-support branch from 573ef7c to f32f40c Compare December 23, 2025 00:39
@robtaylor
robtaylor force-pushed the allow-analog-in-conditionals branch 2 times, most recently from ac1a82d to e3617c8 Compare December 24, 2025 01:33
@robtaylor
robtaylor force-pushed the allow-analog-in-conditionals branch 2 times, most recently from eedcee9 to f8505dd Compare January 9, 2026 02:30
robtaylor and others added 4 commits January 9, 2026 02:35
@robtaylor @claude
Add support for hierarchical module instantiation syntax
e48013c 
This adds parsing and HIR support for Verilog-A module instantiation syntax:
  module_name #(.param(value)) instance_name (port1, port2);

This syntax is used in some foundry PDK models (e.g., GF130 ESD models)
to instantiate primitive modules like resistors and capacitors with
parameter overrides.

Changes:
- Add ModuleInst grammar to veriloga.ungram with ParamAssignments and
  PortConnections
- Implement parser grammar with lookahead to distinguish module
  instantiation from net declarations
- Add ModuleInstItem HIR type to store instance name, module type,
  parameter assignments, and port connections
- Add HIR lowering for module instances
- Module instances are recorded but don't participate in name resolution
  (they will be processed during elaboration/flattening)

Note: This is parsing support only. The actual instantiation/flattening
of modules is not implemented - the instances are simply stored in the
HIR for potential future use.

🤖 Generated with [Claude Code](https://claude.com/claude-code)

Co-Authored-By: Claude <noreply@anthropic.com>
@robtaylor @claude
Add --allow-builtin-primitives CLI flag
a8f9e2e 
Add a CLI flag to enable built-in primitive module support (resistor,
capacitor, inductor). This feature is now disabled by default to maintain
compatibility with models that may define their own modules with these
names.

Changes:
- Add ALLOW_BUILTIN_PRIMITIVES constant and CLI argument in cli_def.rs
- Add allow_builtin_primitives field to CompilationOpts
- Add allow_builtin_primitives() salsa input to HirDefDB
- Gate primitive lowering in body.rs on the flag
- Update tests to set the flag where needed
- Integration tests enable the flag for BUILTIN_PRIMITIVES test dir

Usage: openvaf-r --allow-builtin-primitives model.va

🤖 Generated with [Claude Code](https://claude.com/claude-code)

Co-Authored-By: Claude <noreply@anthropic.com>
@robtaylor @claude
Fix code formatting with nightly rustfmt
fea4cce 
Apply nightly rustfmt formatting to satisfy CI requirements.

🤖 Generated with [Claude Code](https://claude.com/claude-code)

Co-Authored-By: Claude <noreply@anthropic.com>
@robtaylor @claude
Move BuiltInPrimitive enum to body/lower.rs
850ad05 
The BuiltInPrimitive enum was in builtin.rs which is auto-generated
by sourcegen. Moving it to body/lower.rs where it's actually used
prevents it from being removed during code generation.

🤖 Generated with [Claude Code](https://claude.com/claude-code)

Co-Authored-By: Claude <noreply@anthropic.com>
@robtaylor
robtaylor force-pushed the builtin-primitive-support branch from f32f40c to eab1d71 Compare January 9, 2026 02:40
robtaylor and others added 2 commits January 9, 2026 23:09
@robtaylor @claude
Fix integration tests for multi-module files
3fd9635 
- Update compile_and_load_with_opts to handle files with multiple modules
- Add OSDI snapshots for BUILTIN_PRIMITIVES and MODULE_INST tests
- Remove unused compile_and_load function

🤖 Generated with [Claude Code](https://claude.com/claude-code)

Co-Authored-By: Claude <noreply@anthropic.com>
@robtaylor @claude
Fix missing imports and add test file for builtin primitives
c86d6ad 
- Add missing imports in body/lower.rs: Name, AssignOp, BinaryOp,
  AstNode, ItemTree, Module, ModuleInstItem, ModuleItem
- Add AstPtr import in item_tree/lower.rs
- Fix duplicate ConstExprValue import in item_tree.rs
- Change ModuleInstItem.param_assignments to store AstPtr<ast::Expr>
  instead of Name to allow proper expression handling
- Add builtin_primitives.va test file with resistor and capacitor
  primitives demonstrating the feature
- Update OSDI snapshot to match test output

🤖 Generated with [Claude Code](https://claude.com/claude-code)

Co-Authored-By: Claude <noreply@anthropic.com>
@robtaylor
robtaylor force-pushed the builtin-primitive-support branch from eab1d71 to c86d6ad Compare January 9, 2026 23:10
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

No reviews

Assignees

No one assigned

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

1 participant

@robtaylor