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9 changes: 1 addition & 8 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -17,22 +17,15 @@ jobs:

include:
# Test MSRV
- rust: 1.71.0
# Should be set to true for >= 1.81.0
test_cortex_m_types: false
- rust: 1.85.0

# Test nightly but don't fail
- rust: nightly
test_cortex_m_types: true
experimental: true
steps:
- uses: actions/checkout@v4
- uses: dtolnay/rust-toolchain@master
with:
toolchain: ${{ matrix.rust }}
- name: Run tests
if: ${{ matrix.test_cortex_m_types }}
run: cargo test --all --exclude cortex-m-rt --exclude testsuite --features cortex-m/critical-section-single-core
- name: Run tests for < 1.81.0 (need to exclude cortex-m-types)
if: ${{ matrix.test_cortex_m_types == false }}
run: cargo test --all --exclude cortex-m-rt --exclude testsuite --exclude cortex-m-types --features cortex-m/critical-section-single-core
2 changes: 1 addition & 1 deletion .github/workflows/clippy.yml
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ jobs:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v4
- uses: dtolnay/rust-toolchain@1.81
- uses: dtolnay/rust-toolchain@1.85
with:
components: clippy
- run: cargo clippy --all --features cortex-m/critical-section-single-core -- --deny warnings
2 changes: 1 addition & 1 deletion .github/workflows/rt-ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ jobs:
continue-on-error: ${{ matrix.experimental || false }}
strategy:
matrix:
rust: [nightly, stable, 1.71.0]
rust: [nightly, stable, 1.85.0]

include:
# Nightly is only for reference and allowed to fail
Expand Down
2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
[workspace]
resolver = "2"
resolver = "3"
members = [
"cortex-m",
"cortex-m-types",
Expand Down
2 changes: 1 addition & 1 deletion cortex-m-rt/CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
from an external device. Note that this relies on the bootloader to have already
copied `.data` to the VMA before relinquishing control.
- Updated references from 'Cortex-M Team' to 'Arm Team'
- Bump MSRV to 1.71
- Bump MSRV to 1.85

## [v0.7.5]

Expand Down
9 changes: 2 additions & 7 deletions cortex-m-rt/Cargo.toml
Original file line number Diff line number Diff line change
@@ -1,9 +1,4 @@
[package]
authors = [
"The Embedded Devices Working Group's Arm Team <cortex-m@teams.rust-embedded.org>",
"Jorge Aparicio <jorge@japaric.io>",
"Hideki Sekine <sekineh@me.com>",
]
categories = ["embedded", "no-std"]
description = "Minimal runtime / startup for Cortex-M microcontrollers"
documentation = "https://docs.rs/cortex-m-rt/"
Expand All @@ -15,8 +10,8 @@ repository = "https://github.com/rust-embedded/cortex-m"
version = "0.7.5"
autoexamples = true
links = "cortex-m-rt" # Prevent multiple versions of cortex-m-rt being linked
edition = "2021"
rust-version = "1.71"
edition = "2024"
rust-version = "1.85"

[dependencies]
cortex-m-rt-macros = { path = "macros", version = "=0.7.5" }
Expand Down
2 changes: 1 addition & 1 deletion cortex-m-rt/README.md
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ This project is developed and maintained by the [Embedded Devices Working Group'

## Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.61.0 and up. It *might*
This crate is guaranteed to compile on stable Rust 1.85 and up. It *might*
compile with older versions but that may change in any new patch release.

## License
Expand Down
7 changes: 3 additions & 4 deletions cortex-m-rt/examples/device.rs
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
//! Manually create the interrupts portion of the vector table

#![deny(unsafe_code)]
#![deny(warnings)]
#![no_main]
#![no_std]
Expand All @@ -22,14 +21,14 @@ pub union Vector {
reserved: usize,
}

extern "C" {
unsafe extern "C" {
fn WWDG();
fn PVD();
}

#[allow(unsafe_code)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
#[unsafe(link_section = ".vector_table.interrupts")]
#[unsafe(no_mangle)]
pub static __INTERRUPTS: [Vector; 3] = [
Vector { handler: WWDG },
Vector { reserved: 0 },
Expand Down
2 changes: 1 addition & 1 deletion cortex-m-rt/examples/hard-fault-trampoline.rs
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ extern crate cortex_m_rt;
extern crate panic_halt;

use core::arch::asm;
use cortex_m_rt::{entry, exception, ExceptionFrame};
use cortex_m_rt::{ExceptionFrame, entry, exception};

// This defines both `HardFault` and `_HardFault`. Both should have
// link_section attributes placing them at the end of the .text section,
Expand Down
2 changes: 1 addition & 1 deletion cortex-m-rt/examples/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
extern crate cortex_m_rt as rt;
extern crate panic_halt;

#[no_mangle]
#[unsafe(no_mangle)]
pub unsafe extern "C" fn main() -> ! {
loop {}
}
2 changes: 1 addition & 1 deletion cortex-m-rt/examples/override-exception.rs
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ extern crate cortex_m_rt as rt;
extern crate panic_halt;

use cortex_m::asm;
use rt::{entry, exception, ExceptionFrame};
use rt::{ExceptionFrame, entry, exception};

#[entry]
fn main() -> ! {
Expand Down
2 changes: 1 addition & 1 deletion cortex-m-rt/examples/unsafe-hard-fault.rs
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
extern crate cortex_m_rt;
extern crate panic_halt;

use cortex_m_rt::{entry, exception, ExceptionFrame};
use cortex_m_rt::{ExceptionFrame, entry, exception};

#[entry]
fn foo() -> ! {
Expand Down
10 changes: 5 additions & 5 deletions cortex-m-rt/examples/unsafety.rs
Original file line number Diff line number Diff line change
Expand Up @@ -7,30 +7,30 @@
extern crate cortex_m_rt;
extern crate panic_halt;

use cortex_m_rt::{entry, exception, ExceptionFrame};
use cortex_m_rt::{ExceptionFrame, entry, exception};

#[entry]
unsafe fn main() -> ! {
foo();
unsafe { foo() };

loop {}
}

#[exception]
unsafe fn DefaultHandler(_irqn: i16) {
foo();
unsafe { foo() };
}

#[exception]
unsafe fn HardFault(_ef: &ExceptionFrame) -> ! {
foo();
unsafe { foo() };

loop {}
}

#[exception]
unsafe fn SysTick() {
foo();
unsafe { foo() };
}

unsafe fn foo() {}
2 changes: 1 addition & 1 deletion cortex-m-rt/examples/warnings.rs
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@
extern crate cortex_m_rt;
extern crate panic_halt;

use cortex_m_rt::{entry, exception, interrupt, pre_init, ExceptionFrame};
use cortex_m_rt::{ExceptionFrame, entry, exception, interrupt, pre_init};

#[allow(non_camel_case_types)]
enum interrupt {
Expand Down
54 changes: 27 additions & 27 deletions cortex-m-rt/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -361,13 +361,13 @@
//! reserved: usize,
//! }
//!
//! extern "C" {
//! unsafe extern "C" {
//! fn Foo();
//! fn Bar();
//! }
//!
//! #[link_section = ".vector_table.interrupts"]
//! #[no_mangle]
//! #[unsafe(link_section = ".vector_table.interrupts")]
//! #[unsafe(no_mangle)]
//! pub static __INTERRUPTS: [Vector; 5] = [
//! // 0-1: Reserved
//! Vector { reserved: 0 },
Expand Down Expand Up @@ -440,14 +440,14 @@
//!
//! [`MaybeUninit`]: https://doc.rust-lang.org/core/mem/union.MaybeUninit.html
//!
//! ```no_run,edition2018
//! ```no_run
//! # extern crate core;
//! use core::mem::MaybeUninit;
//!
//! const STACK_SIZE: usize = 8 * 1024;
//! const NTHREADS: usize = 4;
//!
//! #[link_section = ".uninit.STACKS"]
//! #[unsafe(link_section = ".uninit.STACKS")]
//! static mut STACKS: MaybeUninit<[[u8; STACK_SIZE]; NTHREADS]> = MaybeUninit::uninit();
//! ```
//!
Expand Down Expand Up @@ -483,10 +483,10 @@
//!
//! You can then use something like this to place a variable into this specific section of memory:
//!
//! ```no_run,edition2018
//! ```no_run
//! # extern crate core;
//! # use core::mem::MaybeUninit;
//! #[link_section=".ccmram.BUFFERS"]
//! #[unsafe(link_section=".ccmram.BUFFERS")]
//! static mut BUF: MaybeUninit<[u8; 1024]> = MaybeUninit::uninit();
//! ```
//!
Expand Down Expand Up @@ -937,7 +937,7 @@ pub use macros::pre_init;
// two copies of cortex-m-rt together, linking will fail. We also declare a links key in
// Cargo.toml which is the more modern way to solve the same problem, but we have to keep
// __ONCE__ around to prevent linking with versions before the links key was added.
#[export_name = "error: cortex-m-rt appears more than once in the dependency graph"]
#[unsafe(export_name = "error: cortex-m-rt appears more than once in the dependency graph")]
#[doc(hidden)]
pub static __ONCE__: () = ();

Expand Down Expand Up @@ -1120,7 +1120,7 @@ impl fmt::Debug for ExceptionFrame {
/// The returned pointer is guaranteed to be 4-byte aligned.
#[inline]
pub fn heap_start() -> *mut u32 {
extern "C" {
unsafe extern "C" {
static mut __sheap: u32;
}

Expand All @@ -1132,27 +1132,27 @@ pub fn heap_start() -> *mut u32 {

// Entry point is Reset.
#[doc(hidden)]
#[cfg_attr(cortex_m, link_section = ".vector_table.reset_vector")]
#[no_mangle]
#[cfg_attr(cortex_m, unsafe(link_section = ".vector_table.reset_vector"))]
#[unsafe(no_mangle)]
pub static __RESET_VECTOR: unsafe extern "C" fn() -> ! = Reset;

#[doc(hidden)]
#[cfg_attr(cortex_m, link_section = ".HardFault.default")]
#[no_mangle]
#[cfg_attr(cortex_m, unsafe(link_section = ".HardFault.default"))]
#[unsafe(no_mangle)]
pub unsafe extern "C" fn HardFault_() -> ! {
#[allow(clippy::empty_loop)]
loop {}
}

#[doc(hidden)]
#[no_mangle]
#[unsafe(no_mangle)]
pub unsafe extern "C" fn DefaultHandler_() -> ! {
#[allow(clippy::empty_loop)]
loop {}
}

#[doc(hidden)]
#[no_mangle]
#[unsafe(no_mangle)]
pub unsafe extern "C" fn DefaultPreInit() {}

/* Exceptions */
Expand Down Expand Up @@ -1187,7 +1187,7 @@ pub enum Exception {
#[doc(hidden)]
pub use self::Exception as exception;

extern "C" {
unsafe extern "C" {
fn Reset() -> !;

fn NonMaskableInt();
Expand Down Expand Up @@ -1224,8 +1224,8 @@ pub union Vector {
}

#[doc(hidden)]
#[cfg_attr(cortex_m, link_section = ".vector_table.exceptions")]
#[no_mangle]
#[cfg_attr(cortex_m, unsafe(link_section = ".vector_table.exceptions"))]
#[unsafe(no_mangle)]
pub static __EXCEPTIONS: [Vector; 14] = [
// Exception 2: Non Maskable Interrupt.
Vector {
Expand Down Expand Up @@ -1284,10 +1284,10 @@ pub static __EXCEPTIONS: [Vector; 14] = [
// to the default handler
#[cfg(all(any(not(feature = "device"), test), not(armv6m), not(armv8m_main)))]
#[doc(hidden)]
#[cfg_attr(cortex_m, link_section = ".vector_table.interrupts")]
#[no_mangle]
#[cfg_attr(cortex_m, unsafe(link_section = ".vector_table.interrupts"))]
#[unsafe(no_mangle)]
pub static __INTERRUPTS: [unsafe extern "C" fn(); 240] = [{
extern "C" {
unsafe extern "C" {
fn DefaultHandler();
}

Expand All @@ -1297,10 +1297,10 @@ pub static __INTERRUPTS: [unsafe extern "C" fn(); 240] = [{
// ARMv8-M Mainline can have up to 480 device specific interrupts
#[cfg(all(not(feature = "device"), armv8m_main))]
#[doc(hidden)]
#[cfg_attr(cortex_m, link_section = ".vector_table.interrupts")]
#[no_mangle]
#[cfg_attr(cortex_m, unsafe(link_section = ".vector_table.interrupts"))]
#[unsafe(no_mangle)]
pub static __INTERRUPTS: [unsafe extern "C" fn(); 480] = [{
extern "C" {
unsafe extern "C" {
fn DefaultHandler();
}

Expand All @@ -1310,10 +1310,10 @@ pub static __INTERRUPTS: [unsafe extern "C" fn(); 480] = [{
// ARMv6-M can only have a maximum of 32 device specific interrupts
#[cfg(all(not(feature = "device"), armv6m))]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
#[unsafe(link_section = ".vector_table.interrupts")]
#[unsafe(no_mangle)]
pub static __INTERRUPTS: [unsafe extern "C" fn(); 32] = [{
extern "C" {
unsafe extern "C" {
fn DefaultHandler();
}

Expand Down
2 changes: 1 addition & 1 deletion cortex-m-semihosting/CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ This project adheres to [Semantic Versioning](http://semver.org/).

## [Unreleased]

- MSRV bumped to 1.60 to align with `embedded-hal` version 1.
- MSRV bumped to 1.85
- Updated references from 'Cortex-M Team' to 'Arm Team'

## [v0.5.0] - 2022-03-01
Expand Down
8 changes: 2 additions & 6 deletions cortex-m-semihosting/Cargo.toml
Original file line number Diff line number Diff line change
@@ -1,8 +1,4 @@
[package]
authors = [
"The Embedded Devices Working Group's Arm Team <cortex-m@teams.rust-embedded.org>",
"Jorge Aparicio <japaricious@gmail.com>",
]
description = "Semihosting for ARM Cortex-M processors"
documentation = "https://docs.rs/cortex-m-semihosting"
keywords = ["semihosting", "arm", "cortex-m"]
Expand All @@ -12,8 +8,8 @@ name = "cortex-m-semihosting"
readme = "README.md"
repository = "https://github.com/rust-embedded/cortex-m"
version = "0.5.0"
edition = "2021"
rust-version = "1.71"
edition = "2024"
rust-version = "1.85"

[features]
jlink-quirks = []
Expand Down
2 changes: 1 addition & 1 deletion cortex-m-semihosting/README.md
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ This project is developed and maintained by the [Embedded Devices Working Group'

# Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.61.0 and up. It *might*
This crate is guaranteed to compile on stable Rust 1.85 and up. It *might*
compile with older versions but that may change in any new patch release.

## License
Expand Down
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