Skip to content

Add support for Hexagon HVX#509

Merged
calebzulawski merged 2 commits intorust-lang:masterfrom
androm3da:bcain/hexagon_hvx
Mar 27, 2026
Merged

Add support for Hexagon HVX#509
calebzulawski merged 2 commits intorust-lang:masterfrom
androm3da:bcain/hexagon_hvx

Conversation

@androm3da
Copy link
Copy Markdown
Contributor

Add vendor module and tests for Qualcomm Hexagon HVX (Hexagon Vector eXtension) SIMD support. HVX provides wide vector operations in either 64-byte (512-bit) or 128-byte (1024-bit) mode.

Note: u8x128/i8x128 types are not included because portable-simd currently limits lane count to 64 (bitmask operations use u64). In 128-byte HVX mode, u8x64 maps to a half-vector (512-bit).

@androm3da
Copy link
Copy Markdown
Contributor Author

androm3da commented Feb 20, 2026

Successor to #500

Note that llvm/llvm-project#182520 causes some problems in some use cases. Hopefully the fix lands soon to make it into 22.x and then into Rust.

@androm3da androm3da marked this pull request as ready for review March 10, 2026 17:17
@androm3da
Copy link
Copy Markdown
Contributor Author

@programmerjake can you review this PR? Or can you give me advice on who should review it?

tyvm

@@ -0,0 +1,433 @@
#![cfg(target_arch = "hexagon")]
Copy link
Copy Markdown
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think these tests are actually largely unnecessary, you should be able to test by running the already existing tests with your -C flags

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed

use crate::simd::*;

#[cfg(target_feature = "hvx-length128b")]
use core::arch::hexagon::v128::HvxVector;
Copy link
Copy Markdown
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I would pull these imports into the modules they're used in. Seems vector lengths should be mutually exclusive but we should still avoid running into that

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed, thanks

from_transmute! { unsafe u64x16 => HvxVector }
from_transmute! { unsafe i64x16 => HvxVector }

// Note: u8x128/i8x128 don't exist in portable-simd
Copy link
Copy Markdown
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Maybe add a FIXME/TODO to make it easier to find in the future

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed

Add vendor module and tests for Qualcomm Hexagon HVX (Hexagon Vector
eXtension) SIMD support. HVX provides wide vector operations in either
64-byte (512-bit) or 128-byte (1024-bit) mode.

Note: u8x128/i8x128 types are not included because portable-simd
currently limits lane count to 64 (bitmask operations use u64).
In 128-byte HVX mode, u8x64 maps to a half-vector (512-bit).
fixup! Add support for Hexagon HVX

Address reviewer feedback:
- Remove hexagon_hvx test file (existing tests suffice with -C flags)
- Move HvxVector imports into their respective cfg modules
- Change u8x128/i8x128 comment to FIXME for discoverability
@rustbot
Copy link
Copy Markdown
Collaborator

rustbot commented Mar 27, 2026

This PR was rebased onto a different master commit. Here's a range-diff highlighting what actually changed.

Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers.

@calebzulawski calebzulawski merged commit 8ada24a into rust-lang:master Mar 27, 2026
53 checks passed
@calebzulawski
Copy link
Copy Markdown
Member

Thank you!

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants