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rustc_target/asm: add LoongArch LSX/LASX inline asm register support #158364

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7cddcd6
rustc_target/asm: add LoongArch LSX/LASX inline asm register support
heiher Jun 23, 2026
748a979
tests/asm: cover LoongArch LSX/LASX register validation
heiher Jun 24, 2026
3f89981
tests/asm: verify LoongArch inline asm register modifiers
heiher Jun 24, 2026
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27 changes: 25 additions & 2 deletions compiler/rustc_codegen_gcc/src/asm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -706,7 +706,9 @@ fn reg_class_to_gcc(reg_class: InlineAsmRegClass) -> &'static str {
unreachable!("clobber-only")
}
InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg) => "f",
InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg)
| InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::vreg)
| InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::xreg) => "f",
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_addr) => "a",
InlineAsmRegClass::M68k(M68kInlineAsmRegClass::reg_data) => "d",
Expand Down Expand Up @@ -815,6 +817,12 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
}
InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg) => cx.type_f32(),
InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::vreg) => {
cx.type_vector(cx.type_i32(), 4)
}
InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::xreg) => {
cx.type_vector(cx.type_i32(), 8)
}
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
Expand Down Expand Up @@ -1013,7 +1021,22 @@ fn modifier_to_gcc(
}
}
InlineAsmRegClass::Hexagon(_) => None,
InlineAsmRegClass::LoongArch(_) => None,
InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::reg) => None,
InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::freg) => modifier,
InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::vreg) => {
if modifier.is_none() {
Some('w')
} else {
modifier
}
}
InlineAsmRegClass::LoongArch(LoongArchInlineAsmRegClass::xreg) => {
if modifier.is_none() {
Some('u')
} else {
modifier
}
}
InlineAsmRegClass::Mips(_) => None,
InlineAsmRegClass::Nvptx(_) => None,
InlineAsmRegClass::PowerPC(PowerPCInlineAsmRegClass::vsreg) => {
Expand Down
23 changes: 21 additions & 2 deletions compiler/rustc_codegen_llvm/src/asm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -709,7 +709,9 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) ->
Hexagon(HexagonInlineAsmRegClass::vreg_pair) => "v",
Hexagon(HexagonInlineAsmRegClass::qreg) => unreachable!("clobber-only"),
LoongArch(LoongArchInlineAsmRegClass::reg) => "r",
LoongArch(LoongArchInlineAsmRegClass::freg) => "f",
LoongArch(LoongArchInlineAsmRegClass::freg)
| LoongArch(LoongArchInlineAsmRegClass::vreg)
| LoongArch(LoongArchInlineAsmRegClass::xreg) => "f",
Mips(MipsInlineAsmRegClass::reg) => "r",
Mips(MipsInlineAsmRegClass::freg) => "f",
Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
Expand Down Expand Up @@ -814,7 +816,22 @@ fn modifier_to_llvm(
}
Amdgpu(_) => None,
Hexagon(_) => None,
LoongArch(_) => None,
LoongArch(LoongArchInlineAsmRegClass::reg) => None,
LoongArch(LoongArchInlineAsmRegClass::freg) => modifier,
LoongArch(LoongArchInlineAsmRegClass::vreg) => {
if modifier.is_none() {
Some('w')
} else {
modifier
}
}
LoongArch(LoongArchInlineAsmRegClass::xreg) => {
if modifier.is_none() {
Some('u')
} else {
modifier
}
}
Mips(_) => None,
Nvptx(_) => None,
PowerPC(PowerPCInlineAsmRegClass::vsreg) => {
Expand Down Expand Up @@ -917,6 +934,8 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'
Hexagon(HexagonInlineAsmRegClass::qreg) => unreachable!("clobber-only"),
LoongArch(LoongArchInlineAsmRegClass::reg) => cx.type_i32(),
LoongArch(LoongArchInlineAsmRegClass::freg) => cx.type_f32(),
LoongArch(LoongArchInlineAsmRegClass::vreg) => cx.type_vector(cx.type_i32(), 4),
LoongArch(LoongArchInlineAsmRegClass::xreg) => cx.type_vector(cx.type_i32(), 8),
Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
Expand Down
3 changes: 3 additions & 0 deletions compiler/rustc_span/src/symbol.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1168,6 +1168,7 @@ symbols! {
lang_items,
large_assignments,
last,
lasx,
lateout,
lazy_normalization_consts,
lazy_type_alias,
Expand Down Expand Up @@ -1225,6 +1226,7 @@ symbols! {
loop_hints,
loop_match,
lr,
lsx,
lt,
m68k,
m68k_target_feature,
Expand Down Expand Up @@ -2365,6 +2367,7 @@ symbols! {
xloop,
xmm_reg,
xop_target_feature,
xreg,
xtensa,
xtensa_target_feature,
yeet_desugar_details,
Expand Down
151 changes: 150 additions & 1 deletion compiler/rustc_target/src/asm/loongarch.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -8,12 +8,19 @@ def_reg_class! {
LoongArch LoongArchInlineAsmRegClass {
reg,
freg,
vreg,
xreg,
}
}

impl LoongArchInlineAsmRegClass {
pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
&[]
match self {
Self::freg => &['w', 'u'],
Self::vreg => &['u'],
Self::xreg => &['w'],
_ => &[],
}
}

pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
Expand All @@ -35,13 +42,35 @@ impl LoongArchInlineAsmRegClass {
pub fn supported_types(
self,
arch: InlineAsmArch,
allow_experimental_reg: bool,
) -> &'static [(InlineAsmType, Option<Symbol>)] {
match (self, arch) {
(Self::reg, InlineAsmArch::LoongArch64) => {
types! { _: I8, I16, I32, I64, F16, F32, F64; }
}
(Self::reg, InlineAsmArch::LoongArch32) => types! { _: I8, I16, I32, F16, F32; },
(Self::freg, _) => types! { f: F16, F32; d: F64; },
(Self::vreg, _) => {
if allow_experimental_reg {
types! {
lsx: F16, F32, F64,
VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4), VecF64(2);
}
} else {
&[]
}
}
(Self::xreg, _) => {
if allow_experimental_reg {
types! {
lasx: F16, F32, F64,
VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4), VecF64(2),
VecI8(32), VecI16(16), VecI32(8), VecI64(4), VecF32(8), VecF64(4);
}
} else {
&[]
}
}
_ => unreachable!("unsupported register class"),
}
}
Expand Down Expand Up @@ -108,6 +137,70 @@ def_regs! {
f29: freg = ["$f29","$fs5"],
f30: freg = ["$f30","$fs6"],
f31: freg = ["$f31","$fs7"],
vr0: vreg = ["$vr0"],
vr1: vreg = ["$vr1"],
vr2: vreg = ["$vr2"],
vr3: vreg = ["$vr3"],
vr4: vreg = ["$vr4"],
vr5: vreg = ["$vr5"],
vr6: vreg = ["$vr6"],
vr7: vreg = ["$vr7"],
vr8: vreg = ["$vr8"],
vr9: vreg = ["$vr9"],
vr10: vreg = ["$vr10"],
vr11: vreg = ["$vr11"],
vr12: vreg = ["$vr12"],
vr13: vreg = ["$vr13"],
vr14: vreg = ["$vr14"],
vr15: vreg = ["$vr15"],
vr16: vreg = ["$vr16"],
vr17: vreg = ["$vr17"],
vr18: vreg = ["$vr18"],
vr19: vreg = ["$vr19"],
vr20: vreg = ["$vr20"],
vr21: vreg = ["$vr21"],
vr22: vreg = ["$vr22"],
vr23: vreg = ["$vr23"],
vr24: vreg = ["$vr24"],
vr25: vreg = ["$vr25"],
vr26: vreg = ["$vr26"],
vr27: vreg = ["$vr27"],
vr28: vreg = ["$vr28"],
vr29: vreg = ["$vr29"],
vr30: vreg = ["$vr30"],
vr31: vreg = ["$vr31"],
xr0: xreg = ["$xr0"],
xr1: xreg = ["$xr1"],
xr2: xreg = ["$xr2"],
xr3: xreg = ["$xr3"],
xr4: xreg = ["$xr4"],
xr5: xreg = ["$xr5"],
xr6: xreg = ["$xr6"],
xr7: xreg = ["$xr7"],
xr8: xreg = ["$xr8"],
xr9: xreg = ["$xr9"],
xr10: xreg = ["$xr10"],
xr11: xreg = ["$xr11"],
xr12: xreg = ["$xr12"],
xr13: xreg = ["$xr13"],
xr14: xreg = ["$xr14"],
xr15: xreg = ["$xr15"],
xr16: xreg = ["$xr16"],
xr17: xreg = ["$xr17"],
xr18: xreg = ["$xr18"],
xr19: xreg = ["$xr19"],
xr20: xreg = ["$xr20"],
xr21: xreg = ["$xr21"],
xr22: xreg = ["$xr22"],
xr23: xreg = ["$xr23"],
xr24: xreg = ["$xr24"],
xr25: xreg = ["$xr25"],
xr26: xreg = ["$xr26"],
xr27: xreg = ["$xr27"],
xr28: xreg = ["$xr28"],
xr29: xreg = ["$xr29"],
xr30: xreg = ["$xr30"],
xr31: xreg = ["$xr31"],
#error = ["$r0","$zero"] =>
"constant zero cannot be used as an operand for inline asm",
#error = ["$r2","$tp"] =>
Expand All @@ -132,4 +225,60 @@ impl LoongArchInlineAsmReg {
) -> fmt::Result {
out.write_str(self.name())
}

pub fn overlapping_regs(self, mut cb: impl FnMut(LoongArchInlineAsmReg)) {
macro_rules! reg_conflicts {
(
$(
$f:ident : $v:ident : $x:ident
),*;
) => {
match self {
$(
Self::$f | Self::$v | Self::$x => {
cb(Self::$f);
cb(Self::$v);
cb(Self::$x);
}
)*
r => cb(r),
}
};
}

reg_conflicts! {
f0 : vr0 : xr0,
f1 : vr1 : xr1,
f2 : vr2 : xr2,
f3 : vr3 : xr3,
f4 : vr4 : xr4,
f5 : vr5 : xr5,
f6 : vr6 : xr6,
f7 : vr7 : xr7,
f8 : vr8 : xr8,
f9 : vr9 : xr9,
f10 : vr10 : xr10,
f11 : vr11 : xr11,
f12 : vr12 : xr12,
f13 : vr13 : xr13,
f14 : vr14 : xr14,
f15 : vr15 : xr15,
f16 : vr16 : xr16,
f17 : vr17 : xr17,
f18 : vr18 : xr18,
f19 : vr19 : xr19,
f20 : vr20 : xr20,
f21 : vr21 : xr21,
f22 : vr22 : xr22,
f23 : vr23 : xr23,
f24 : vr24 : xr24,
f25 : vr25 : xr25,
f26 : vr26 : xr26,
f27 : vr27 : xr27,
f28 : vr28 : xr28,
f29 : vr29 : xr29,
f30 : vr30 : xr30,
f31 : vr31 : xr31;
}
}
}
4 changes: 2 additions & 2 deletions compiler/rustc_target/src/asm/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -474,7 +474,7 @@ impl InlineAsmReg {
Self::RiscV(_) => cb(self),
Self::PowerPC(r) => r.overlapping_regs(|r| cb(Self::PowerPC(r))),
Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
Self::LoongArch(_) => cb(self),
Self::LoongArch(r) => r.overlapping_regs(|r| cb(Self::LoongArch(r))),
Self::Mips(_) => cb(self),
Self::S390x(r) => r.overlapping_regs(|r| cb(Self::S390x(r))),
Self::Sparc(_) => cb(self),
Expand Down Expand Up @@ -655,7 +655,7 @@ impl InlineAsmRegClass {
Self::Nvptx(r) => r.supported_types(arch).into(),
Self::PowerPC(r) => r.supported_types(arch).into(),
Self::Hexagon(r) => r.supported_types(arch).into(),
Self::LoongArch(r) => r.supported_types(arch).into(),
Self::LoongArch(r) => r.supported_types(arch, allow_experimental_reg).into(),
Self::Mips(r) => r.supported_types(arch).into(),
Self::S390x(r) => r.supported_types(arch).into(),
Self::Sparc(r) => r.supported_types(arch).into(),
Expand Down
13 changes: 13 additions & 0 deletions src/doc/unstable-book/src/language-features/asm-experimental-reg.md
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Expand Up @@ -12,6 +12,8 @@ This tracks support for additional registers in architectures where inline assem

| Architecture | Register class | Registers | LLVM constraint code |
| ------------ | -------------- | --------- | -------------------- |
| LoongArch | `vreg` | `$vr[0-31]` | `f` |
| LoongArch | `xreg` | `$xr[0-31]` | `f` |

## Register class supported types

Expand All @@ -20,11 +22,16 @@ This tracks support for additional registers in architectures where inline assem
| x86 | `xmm_reg` | `sse` | `i128` |
| x86 | `ymm_reg` | `avx` | `i128` |
| x86 | `zmm_reg` | `avx512f` | `i128` |
| LoongArch | `vreg` | `lsx` | `f32`, `f64`, <br> `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4`, `f64x2` |
| LoongArch | `xreg` | `lasx` | `f32`, `f64`, <br> `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4`, `f64x2`, <br> `i8x32`, `i16x16`, `i32x8`, `i64x4`, `f32x8`, `f64x4` |

## Register aliases

| Architecture | Base register | Aliases |
| ------------ | ------------- | ------- |
| LoongArch | `$f[0-7]` | `$fa[0-7]`, `$vr[0-7]`, `$xr[0-7]` |
| LoongArch | `$f[8-23]` | `$ft[0-15]`, `$vr[8-23]`, `$xr[8-23]` |
| LoongArch | `$f[24-31]` | `$fs[0-7]`, `$vr[24-31]`, `$xr[24-31]` |

## Unsupported registers

Expand All @@ -35,3 +42,9 @@ This tracks support for additional registers in architectures where inline assem

| Architecture | Register class | Modifier | Example output | LLVM modifier |
| ------------ | -------------- | -------- | -------------- | ------------- |
| LoongArch | `freg` | `w` | `$vr0` | `w` |
| LoongArch | `freg` | `u` | `$xr0` | `u` |
| LoongArch | `vreg` | None | `$vr0` | `w` |
| LoongArch | `vreg` | `u` | `$xr0` | `u` |
| LoongArch | `xreg` | None | `$xr0` | `u` |
| LoongArch | `xreg` | `w` | `$vr0` | `w` |
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