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use intrinsics::simd for aarch64 deinterleaving loads #2025

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Merged
folkertdev merged 5 commits into from
Feb 18, 2026
+166 −301
Merged

use intrinsics::simd for aarch64 deinterleaving loads #2025

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7fec806
lock stdout when printing a intrinsic test failure
folkertdev Feb 14, 2026
7ee9c77
use `intrinsics::simd` for aarch64 deinterleaving loads
folkertdev Feb 14, 2026
f2a3de2
neon `ld3`
folkertdev Feb 14, 2026
1ccf7b7
neon `ld4`
folkertdev Feb 14, 2026
8ba8329
neon `ld1`
folkertdev Feb 14, 2026
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27 changes: 3 additions & 24 deletions crates/core_arch/src/aarch64/neon/generated.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -11652,14 +11652,7 @@ pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld2.v1f64.p0"
)]
fn _vld2_f64(ptr: *const float64x1_t) -> float64x1x2_t;
}
_vld2_f64(a as _)
crate::ptr::read_unaligned(a.cast())
}
#[doc = "Load multiple 2-element structures to two registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"]
Expand Down Expand Up @@ -12031,14 +12024,7 @@ pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld3.v1f64.p0"
)]
fn _vld3_f64(ptr: *const float64x1_t) -> float64x1x3_t;
}
_vld3_f64(a as _)
crate::ptr::read_unaligned(a.cast())
}
#[doc = "Load multiple 3-element structures to three registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"]
Expand Down Expand Up @@ -12442,14 +12428,7 @@ pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld4.v1f64.p0"
)]
fn _vld4_f64(ptr: *const float64x1_t) -> float64x1x4_t;
}
_vld4_f64(a as _)
crate::ptr::read_unaligned(a.cast())
}
#[doc = "Load multiple 4-element structures to four registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"]
Expand Down
198 changes: 22 additions & 176 deletions crates/core_arch/src/arm_shared/neon/generated.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -22036,14 +22036,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld3.v4f16.p0"
)]
fn _vld3_f16(ptr: *const f16) -> float16x4x3_t;
}
_vld3_f16(a as _)
crate::core_arch::macros::deinterleaving_load!(f16, 4, 3, a)
}
#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
Expand All @@ -22060,14 +22053,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld3.v8f16.p0"
)]
fn _vld3q_f16(ptr: *const f16) -> float16x8x3_t;
}
_vld3q_f16(a as _)
crate::core_arch::macros::deinterleaving_load!(f16, 8, 3, a)
}
#[doc = "Load multiple 3-element structures to three registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
Expand All @@ -22079,14 +22065,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
#[cfg(not(target_arch = "arm"))]
#[cfg_attr(test, assert_instr(ld3))]
pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld3.v2f32.p0"
)]
fn _vld3_f32(ptr: *const float32x2_t) -> float32x2x3_t;
}
_vld3_f32(a as _)
crate::core_arch::macros::deinterleaving_load!(f32, 2, 3, a)
}
#[doc = "Load multiple 3-element structures to three registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
Expand All @@ -22098,14 +22077,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
#[cfg(not(target_arch = "arm"))]
#[cfg_attr(test, assert_instr(ld3))]
pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld3.v4f32.p0"
)]
fn _vld3q_f32(ptr: *const float32x4_t) -> float32x4x3_t;
}
_vld3q_f32(a as _)
crate::core_arch::macros::deinterleaving_load!(f32, 4, 3, a)
}
#[doc = "Load multiple 3-element structures to three registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
Expand All @@ -22117,14 +22089,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
#[cfg(not(target_arch = "arm"))]
#[cfg_attr(test, assert_instr(ld3))]
pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld3.v8i8.p0"
)]
fn _vld3_s8(ptr: *const int8x8_t) -> int8x8x3_t;
}
_vld3_s8(a as _)
crate::core_arch::macros::deinterleaving_load!(i8, 8, 3, a)
}
#[doc = "Load multiple 3-element structures to three registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
Expand All @@ -22136,14 +22101,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
#[cfg(not(target_arch = "arm"))]
#[cfg_attr(test, assert_instr(ld3))]
pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld3.v16i8.p0"
)]
fn _vld3q_s8(ptr: *const int8x16_t) -> int8x16x3_t;
}
_vld3q_s8(a as _)
crate::core_arch::macros::deinterleaving_load!(i8, 16, 3, a)
}
#[doc = "Load multiple 3-element structures to three registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
Expand All @@ -22155,14 +22113,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
#[cfg(not(target_arch = "arm"))]
#[cfg_attr(test, assert_instr(ld3))]
pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld3.v4i16.p0"
)]
fn _vld3_s16(ptr: *const int16x4_t) -> int16x4x3_t;
}
_vld3_s16(a as _)
crate::core_arch::macros::deinterleaving_load!(i16, 4, 3, a)
}
#[doc = "Load multiple 3-element structures to three registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
Expand All @@ -22174,14 +22125,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
#[cfg(not(target_arch = "arm"))]
#[cfg_attr(test, assert_instr(ld3))]
pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld3.v8i16.p0"
)]
fn _vld3q_s16(ptr: *const int16x8_t) -> int16x8x3_t;
}
_vld3q_s16(a as _)
crate::core_arch::macros::deinterleaving_load!(i16, 8, 3, a)
}
#[doc = "Load multiple 3-element structures to three registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
Expand All @@ -22193,14 +22137,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
#[cfg(not(target_arch = "arm"))]
#[cfg_attr(test, assert_instr(ld3))]
pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld3.v2i32.p0"
)]
fn _vld3_s32(ptr: *const int32x2_t) -> int32x2x3_t;
}
_vld3_s32(a as _)
crate::core_arch::macros::deinterleaving_load!(i32, 2, 3, a)
}
#[doc = "Load multiple 3-element structures to three registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
Expand All @@ -22212,14 +22149,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
#[cfg(not(target_arch = "arm"))]
#[cfg_attr(test, assert_instr(ld3))]
pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld3.v4i32.p0"
)]
fn _vld3q_s32(ptr: *const int32x4_t) -> int32x4x3_t;
}
_vld3q_s32(a as _)
crate::core_arch::macros::deinterleaving_load!(i32, 4, 3, a)
}
#[doc = "Load multiple 3-element structures to three registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
Expand Down Expand Up @@ -23039,14 +22969,7 @@ pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t {
#[cfg(not(target_arch = "arm"))]
#[cfg_attr(test, assert_instr(nop))]
pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld3.v1i64.p0"
)]
fn _vld3_s64(ptr: *const int64x1_t) -> int64x1x3_t;
}
_vld3_s64(a as _)
crate::ptr::read_unaligned(a.cast())
}
#[doc = "Load multiple 3-element structures to three registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
Expand Down Expand Up @@ -24413,14 +24336,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld4.v4f16.p0"
)]
fn _vld4_f16(ptr: *const f16) -> float16x4x4_t;
}
_vld4_f16(a as _)
crate::core_arch::macros::deinterleaving_load!(f16, 4, 4, a)
}
#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
Expand All @@ -24436,14 +24352,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld4.v8f16.p0"
)]
fn _vld4q_f16(ptr: *const f16) -> float16x8x4_t;
}
_vld4q_f16(a as _)
crate::core_arch::macros::deinterleaving_load!(f16, 8, 4, a)
}
#[doc = "Load multiple 4-element structures to four registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
Expand All @@ -24455,14 +24364,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ld4))]
pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld4.v2f32.p0"
)]
fn _vld4_f32(ptr: *const float32x2_t) -> float32x2x4_t;
}
_vld4_f32(a as _)
crate::core_arch::macros::deinterleaving_load!(f32, 2, 4, a)
}
#[doc = "Load multiple 4-element structures to four registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
Expand All @@ -24474,14 +24376,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ld4))]
pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld4.v4f32.p0"
)]
fn _vld4q_f32(ptr: *const float32x4_t) -> float32x4x4_t;
}
_vld4q_f32(a as _)
crate::core_arch::macros::deinterleaving_load!(f32, 4, 4, a)
}
#[doc = "Load multiple 4-element structures to four registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
Expand All @@ -24493,14 +24388,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ld4))]
pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld4.v8i8.p0"
)]
fn _vld4_s8(ptr: *const int8x8_t) -> int8x8x4_t;
}
_vld4_s8(a as _)
crate::core_arch::macros::deinterleaving_load!(i8, 8, 4, a)
}
#[doc = "Load multiple 4-element structures to four registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
Expand All @@ -24512,14 +24400,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ld4))]
pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld4.v16i8.p0"
)]
fn _vld4q_s8(ptr: *const int8x16_t) -> int8x16x4_t;
}
_vld4q_s8(a as _)
crate::core_arch::macros::deinterleaving_load!(i8, 16, 4, a)
}
#[doc = "Load multiple 4-element structures to four registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
Expand All @@ -24531,14 +24412,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ld4))]
pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld4.v4i16.p0"
)]
fn _vld4_s16(ptr: *const int16x4_t) -> int16x4x4_t;
}
_vld4_s16(a as _)
crate::core_arch::macros::deinterleaving_load!(i16, 4, 4, a)
}
#[doc = "Load multiple 4-element structures to four registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
Expand All @@ -24550,14 +24424,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ld4))]
pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld4.v8i16.p0"
)]
fn _vld4q_s16(ptr: *const int16x8_t) -> int16x8x4_t;
}
_vld4q_s16(a as _)
crate::core_arch::macros::deinterleaving_load!(i16, 8, 4, a)
}
#[doc = "Load multiple 4-element structures to four registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
Expand All @@ -24569,14 +24436,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ld4))]
pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld4.v2i32.p0"
)]
fn _vld4_s32(ptr: *const int32x2_t) -> int32x2x4_t;
}
_vld4_s32(a as _)
crate::core_arch::macros::deinterleaving_load!(i32, 2, 4, a)
}
#[doc = "Load multiple 4-element structures to four registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
Expand All @@ -24588,14 +24448,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ld4))]
pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld4.v4i32.p0"
)]
fn _vld4q_s32(ptr: *const int32x4_t) -> int32x4x4_t;
}
_vld4q_s32(a as _)
crate::core_arch::macros::deinterleaving_load!(i32, 4, 4, a)
}
#[doc = "Load multiple 4-element structures to four registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
Expand Down Expand Up @@ -25456,14 +25309,7 @@ pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t {
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(nop))]
pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
unsafe extern "unadjusted" {
#[cfg_attr(
any(target_arch = "aarch64", target_arch = "arm64ec"),
link_name = "llvm.aarch64.neon.ld4.v1i64.p0"
)]
fn _vld4_s64(ptr: *const int64x1_t) -> int64x1x4_t;
}
_vld4_s64(a as _)
crate::ptr::read_unaligned(a.cast())
}
#[doc = "Load multiple 4-element structures to four registers"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
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