qboot: enable the MTRRs, write-back by default - #75
Merged
Merged
Conversation
Stock qboot leaves the MTRRs disabled, and Linux maps every range it memremaps write-back but does not know as RAM uncached-minus: a virtio-pmem region read at 8.3 MB/s where SeaBIOS, which programs them, gives 1.1 GB/s (lab runs 36818224412, 36818721809). mtrr.patch does what SeaBIOS does on the boot CPU: enabled, write-back by default, the 32-bit PCI hole from the top of low RAM to 4 GiB uncacheable. A firmware change, so a new machine fingerprint. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
This was referenced Oct 1, 2026
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Stock qboot leaves the MTRRs disabled, and Linux maps every range it
memremaps write-back but does not know as RAM uncached-minus: a
virtio-pmem region read at 8.3 MB/s where SeaBIOS, which programs them,
gives 1.1 GB/s (lab runs 36818224412, 36818721809). mtrr.patch does
what SeaBIOS does on the boot CPU: enabled, write-back by default, the
32-bit PCI hole from the top of low RAM to 4 GiB uncacheable.
A firmware change, so a new machine fingerprint.
Boot time and the pmem read are measured on construct before merge.
🤖 Generated with Claude Code
Need help on this PR? Tag
@codesmith-botwith what you need. Autofix is disabled.