Check-in some changes to run the kernels correctly by Jackcuii · Pull Request #323 · tancheng/VectorCGRA

Jackcuii · 2026-07-12T16:24:59Z

No description provided.

…rnels

- Add CgraRTL_relu4x4_test_from_yaml.py: ReLU kernel test on 4x4 Mesh CGRA using relu.yaml compiled kernel config (II=5, 32 iterations) - Fix script_generator.py: swap STORE src_operands to match MemUnitRTL hardware expectation (in0=address, in1=data vs YAML order [data, addr])

…amls

…flag Bug #1 - CrossbarRTL all-or-nothing: Stale prologued data blocked entire crossbar - Mask recv_valid_vector, exclude prologued from send/recv_required_vector - Gate changed: recv_valid_or_prologue_allowing_vector Bug #2 - PhiRTL shared first flag: Multiple PHI_START on same tile failed - Detect iteration wrap via ctrl_addr, clear s.first only at boundaries - Added prev_ctrl_addr tracking Tests: ReLU 379 cycles (pass), SpMV 759 cycles (pass)

…rnels

Jackcuii · 2026-07-18T15:35:53Z

Update: The reason of CI test fail is the invalid var that Verilog not support

what is the invalid var you are referring to?

Oh sorry It is a typo, I mean char😂

tancheng · 2026-07-18T16:10:33Z

Hi @Jackcuii, can you resolve the comments if you have bandwidth? I would like to merge some register bank related fixes after yours: #322

Hi Sir Tan, I was working on it～ However I caught a fever yesterday 🥵. Hopefully I will be better and back tomorrow.

Ah, take care, get better soon!

tancheng · 2026-07-23T01:03:07Z

+        s.recv_data_from_routing_crossbar[i].rdy @= \
+            (s.inport_opt.operation == OPT_NAH) | \
+            (s.inport_opt.fu_in[i] == 0) | \
+            reg_towards_fu | \
+            s.send_data_to_fu[i].rdy


@yyan7223 does this make sense to you?

tancheng · 2026-07-23T01:04:37Z

@yyan7223 can you plz take a look at this change?

tancheng · 2026-07-24T03:55:32Z

Hi @Jackcuii, as long as you can resolve my comments, it should be okay to check in. Plz try to resolve them ASAP. Thanks!

Jackcuii · 2026-07-25T02:27:34Z

Hi @Jackcuii, as long as you can resolve my comments, it should be okay to check in. Plz try to resolve them ASAP. Thanks!

Okay~ I am checking in the logics the comments mentioned in the branch one by one to make sure all the yaml tests can still pass. It is somehow black-boxed😂

tancheng · 2026-07-27T00:37:21Z

Hi @Jackcuii, as long as you can resolve my comments, it should be okay to check in. Plz try to resolve them ASAP. Thanks!

Okay~ I am checking in the logics the comments mentioned in the branch one by one to make sure all the yaml tests can still pass. It is somehow black-boxed😂

I understand that. Can you then ask your agent to apply my suggestions to see whether it works?

Jackcuii · 2026-07-29T17:46:59Z

Sadly some comments will cause some tests to fail, I am working on it

Jackcuii · 2026-07-29T17:48:21Z

new TODO: merge #322 to this branch after folks' reviews

tancheng · 2026-07-29T18:45:53Z

new TODO: merge #322 to this branch after folks' reviews

I just merged it

tancheng · 2026-08-08T01:11:04Z

@Jackcuii I remember you mentioned that you would update the tests, and double-check the last one finished or not?

So then we can review again and merge this?

…aster

Jackcuii · 2026-08-09T13:51:58Z

@Jackcuii I remember you mentioned that you would update the tests, and double-check the last one finished or not?

So then we can review again and merge this?

omg I just found I did not push all the commits 🤣 here they come.

Some logics have been changed to merge with main 🫠

tancheng · 2026-08-13T05:20:44Z

Hi @Jackcuii, #330 is merged, plz sync :-)

# Conflicts: # mem/register_cluster/RegisterBankRTL.py

tancheng · 2026-08-15T02:49:34Z

Hi @Jackcuii, any update :-) ?

Jackcuii · 2026-08-19T16:58:51Z

Hi @Jackcuii, any update :-) ?

Hi Sir Tan, the hacky logics are removed and tests are passed. But Yosys seems to fail this time ... checking

tancheng · 2026-08-19T18:33:43Z

Why do we need to touch this folder?

Let me check it out, seems related to the Yosys check

tancheng · 2026-08-19T18:35:57Z

  field_dict[kAttrReadRegIdx] = [RegIdxType for _ in range(num_fu_inports)]
+  # One means the next scheduled access to this register needs a live version.
+  # A feedback write replaces it; a predicated-away write leaves it unchanged.
+  field_dict[kAttrReadRegRetain] = [mk_bits(1) for _ in range(num_fu_inports)]


This new filed of read_reg_retain is suspicious... What is it used for? Can we avoid adding it?

Any update on this @Jackcuii?

Sorry Sir Tan I am moving to Swizterland these days... 🫠

It seems to be necessary:

read_reg_retain marks whether the register version read by the current ctrl
step has another scheduled reader before the next write. The register bank
only sees the current ctrl word, so without this information it cannot
distinguish a non-final read from the final read. Clearing on every read
breaks values shared by multiple ctrl steps, while never clearing blocks the
next write. The script generator computes this bit from the cyclic per-
register read/write order; it is not kernel-specific. We could avoid
exposing the field only by adding control-memory lookahead/reference
counting in hardware or by rewriting the schedule, both of which are
substantially more complex.

🤔 maybe need to dive into the register?

I don't get what it wants to achieve. "Clearing on every read breaks values shared by multiple ctrl steps"...

in which scenario/kernel it needs this "fix"? We already and skid buffer in master and enable holding reg's consumption if current ctrl has other consumers..

@Jackcuii Can we revert the register related change, and exclude the failed test? We can investigate the register related issue in a standalone PR. How does this sound?

It breaks GEMM and GEMV, others are good
#326
(To make sure we still have a all-pass version for AE, this old branch is kept)
I somehow know the reason (bad habit x_x, did not record it carefully when I debugged a few month ago)

well, I still see _retain in #336. For #326, my intention is you can check in all changes from this PR except the changes related to the _retain...

Any update on #336 (review)?

Hi Sir Tan I think the left _retains are leftover and not function at all. I just remove them :)

Cool, thanks! Can you also sync that PR with master for submission?

Jackcuii and others added 30 commits March 29, 2026 09:05

merge master

7b13b42

Merge remote-tracking branch 'origin/master' into fulfill-compiled-ke…

4997351

…rnels

add visualizer for debugging

2142819

add trace support

f0e5b7a

fix multiple bugs in script_generator

4e11bcb

add compiled kernel files

723899d

add compiled kernels

b2c388b

add grant_once_const

15407d6

fix opcode collision

b47f363

add relu kernel

da6255f

support SGE_CONST

4df8179

Update final version kernels

bf6a598

add axpy/histogram

97e0227

add DIV_CONST, support multi-cycle prologue, update visualizer, add y…

c8cd631

…amls

spmv and assist files

7f1af27

assist files

5117354

Merge remote-tracking branch 'origin/master' into fulfill-compiled-ke…

66f84f8

…rnels

add conv

4a87991

fix collision of opcode

6196bf5

add gemm and gemv (Note new genarator may not apply to gemv)

1e4bc24

add sad & fix bugs

53365b4

fix axpy

9390d1f

add timeline plot

64487a3

fix cycle gap

fe8b7f0

update histo input

4b78fc6

fix generator

dd7c62b

fix signed compare

86397d3

add drain cycles

b727f99

Jackcuii added 2 commits July 22, 2026 10:48

Move constant handling from PhiRTL to ConstRTL

ebde1ec

Normalize RegisterClusterRTL line endings

49b8331

tancheng reviewed Jul 23, 2026

View reviewed changes

tancheng reviewed Jul 24, 2026

View reviewed changes

Comment thread mem/register_cluster/RegisterClusterRTL.py Outdated

tancheng reviewed Jul 24, 2026

View reviewed changes

Comment thread noc/CrossbarRTL.py Outdated

Comment thread noc/CrossbarRTL.py Outdated

Comment thread noc/CrossbarRTL.py Outdated

Comment thread noc/CrossbarRTL.py Outdated

Comment thread mem/register_cluster/RegisterClusterRTL.py Outdated

Bohan Cui added 2 commits August 5, 2026 19:58

Fix shuffled FU input lane readiness

acf0ebe

Clarify prologue crossbar signal names

e6d089d

Bohan Cui added 3 commits August 9, 2026 06:36

Merge origin/master into kernel-submit

c5367cb

Merge remote-tracking branch 'origin/master' into codex/merge-pr323-m…

7a05e13

…aster

Fix RegisterCluster RTLIR translation

7c32b89

tancheng mentioned this pull request Aug 10, 2026

Fix incorrect first outputs in GEMV, Histogram, and AXPY coredac/CGRA-SoC#3

Open

tancheng reviewed Aug 11, 2026

View reviewed changes

Comment thread mem/register_cluster/RegisterBankRTL.py Outdated

Bohan Cui added 2 commits August 13, 2026 09:26

Unify register token lifetimes across generated kernels

721261b

Merge remote-tracking branch 'origin/master' into HEAD

798aaf5

# Conflicts: # mem/register_cluster/RegisterBankRTL.py

Bohan Cui added 2 commits August 19, 2026 12:46

Fix pure SV fixtures after control packet update

a835701

Sync pure SV FIR fixture with Python reference

366bdd7

tancheng reviewed Aug 19, 2026

View reviewed changes

Conversation

Jackcuii commented Jul 12, 2026

Uh oh!

Jackcuii commented Jul 18, 2026

Uh oh!

tancheng commented Jul 18, 2026

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

tancheng commented Jul 24, 2026

Uh oh!

Jackcuii commented Jul 25, 2026

Uh oh!

tancheng commented Jul 27, 2026

Uh oh!

Jackcuii commented Jul 29, 2026

Uh oh!

Jackcuii commented Jul 29, 2026

Uh oh!

tancheng commented Jul 29, 2026

Uh oh!

tancheng commented Aug 8, 2026

Uh oh!

Jackcuii commented Aug 9, 2026

Uh oh!

Uh oh!

tancheng commented Aug 13, 2026

Uh oh!

tancheng commented Aug 15, 2026

Uh oh!

Jackcuii commented Aug 19, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Jackcuii Aug 24, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Jackcuii Aug 30, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

3 participants

Jackcuii commented Aug 19, 2026 •

edited

Loading

Jackcuii Aug 24, 2026 •

edited

Loading

Jackcuii Aug 30, 2026 •

edited

Loading