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stm32: update lib/stm32-svd (stm32-rs @2026-02-21); adjust files in target, src/machine|runtime, where necessary #5218

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Merged
deadprogram merged 5 commits into from
Feb 26, 2026
Merged

stm32: update lib/stm32-svd (stm32-rs @2026-02-21); adjust files in target, src/machine|runtime, where necessary #5218

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95fb046
lib/stm32-svd: update submodule
knieriem Feb 25, 2026
4776e4a
targets/nucleo-f722ze.json: add build-tag stm32f722, change stm32f7x2…
knieriem Nov 28, 2025
ea7989d
targets/swan: rename group build tag stm32l4x5 => stm32l4y5 to avoid …
knieriem Feb 23, 2026
9326152
machine: sync stm32g0 with updated stm32 device files
knieriem Feb 23, 2026
c49d0ba
machine: stm32l0x1,l0x2: TIM: adapt to 32-bit register access
knieriem Feb 23, 2026
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2 changes: 1 addition & 1 deletion lib/stm32-svd
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Submodule stm32-svd updated 161 files
2 changes: 1 addition & 1 deletion src/machine/machine_stm32_adc_g0.go
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Original file line number Diff line number Diff line change
Expand Up @@ -123,7 +123,7 @@ func (a ADC) Get() uint16 {

// Select the channel to convert using CHSELR
// CHSELR uses a bitfield where bit N = 1 enables channel N
stm32.ADC.CHSELR.Set(1 << ch)
stm32.ADC.CHSELR0.Set(1 << ch)

// Wait for channel configuration ready
for stm32.ADC.GetISR_CCRDY() == 0 {
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2 changes: 1 addition & 1 deletion src/machine/machine_stm32_uart.go
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
//go:build stm32 && !stm32g0
//go:build stm32

package machine

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6 changes: 3 additions & 3 deletions src/machine/machine_stm32g0.go
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Original file line number Diff line number Diff line change
Expand Up @@ -230,7 +230,7 @@ func (uart *UART) getBaudRateDivisor(baudRate uint32) uint32 {
func (uart *UART) setRegisters() {
uart.rxReg = &uart.Bus.RDR
uart.txReg = &uart.Bus.TDR
uart.statusReg = &uart.Bus.ISR_FIFO_ENABLED
uart.statusReg = &uart.Bus.ISR
uart.txEmptyFlag = stm32.USART_ISR_TXE
}

Expand Down Expand Up @@ -508,7 +508,7 @@ func (t *TIM) registerUPInterrupt() interrupt.Interrupt {
case &TIM3:
return interrupt.New(stm32.IRQ_TIM3_TIM4, TIM3.handleUPInterrupt)
case &TIM6:
return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleUPInterrupt)
return interrupt.New(stm32.IRQ_TIM6_DAC_LPTIM1, TIM6.handleUPInterrupt)
case &TIM7:
return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt)
case &TIM14:
Expand All @@ -533,7 +533,7 @@ func (t *TIM) registerOCInterrupt() interrupt.Interrupt {
case &TIM3:
return interrupt.New(stm32.IRQ_TIM3_TIM4, TIM3.handleOCInterrupt)
case &TIM6:
return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleOCInterrupt)
return interrupt.New(stm32.IRQ_TIM6_DAC_LPTIM1, TIM6.handleOCInterrupt)
case &TIM7:
return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt)
case &TIM14:
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86 changes: 0 additions & 86 deletions src/machine/machine_stm32g0_uart.go
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This file was deleted.

4 changes: 2 additions & 2 deletions src/machine/machine_stm32l0x1.go
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Original file line number Diff line number Diff line change
Expand Up @@ -188,8 +188,8 @@ func (t *TIM) enableMainOutput() {
// nothing to do - no BDTR register
}

type arrtype = uint16
type arrRegType = volatile.Register16
type arrtype = uint32
type arrRegType = volatile.Register32

const (
ARR_MAX = 0x10000
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4 changes: 2 additions & 2 deletions src/machine/machine_stm32l0x2.go
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Original file line number Diff line number Diff line change
Expand Up @@ -245,8 +245,8 @@ func (t *TIM) enableMainOutput() {
// nothing to do - no BDTR register
}

type arrtype = uint16
type arrRegType = volatile.Register16
type arrtype = uint32
type arrRegType = volatile.Register32

const (
ARR_MAX = 0x10000
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2 changes: 1 addition & 1 deletion src/machine/machine_stm32l4x5.go
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
//go:build stm32l4x5
//go:build stm32l4y5

package machine

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2 changes: 1 addition & 1 deletion src/runtime/runtime_stm32l4x5.go
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
//go:build stm32 && stm32l4x5
//go:build stm32 && stm32l4y5

package runtime

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4 changes: 2 additions & 2 deletions targets/nucleo-f722ze.json
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Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
{
"inherits": ["cortex-m7"],
"build-tags": ["nucleof722ze", "stm32f7x2", "stm32f7", "stm32"],
"build-tags": ["nucleof722ze", "stm32f722", "stm32f7x2", "stm32f7", "stm32"],
"serial": "uart",
"linkerscript": "targets/stm32f7x2zetx.ld",
"extra-files": [
"src/device/stm32/stm32f7x2.s"
"src/device/stm32/stm32f722.s"
],
"flash-method": "openocd",
"openocd-interface": "stlink-v2-1",
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2 changes: 1 addition & 1 deletion targets/swan.json
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
{
"inherits": ["cortex-m4"],
"build-tags": ["swan", "stm32l4r5", "stm32l4x5", "stm32l4", "stm32"],
"build-tags": ["swan", "stm32l4r5", "stm32l4y5", "stm32l4", "stm32"],
"serial": "uart",
"linkerscript": "targets/stm32l4x5.ld",
"extra-files": [
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