clock-gating

A modular, open-source Power Management Unit (PMU) integrated into the PULP Croc SoC — an open-source RISC-V SoC based on the CVE2 (Ibex) core. Implements clock gating and power gating via UPF (IEEE 1801), using a fully open-source RTL-to-GDSII flow.

A comprehensive clock management IP core with multiple divider types and glitch-free switching

Instruction-Aware Fine-Grained Clock Gating in an Open Source RV32I Processor using Verilog HDL.

A configurable Arithmetic Logic Unit (ALU) supporting 12 operations with parameterized data width. Designed with low-power techniques including clock gating and operand isolation. Simulated using Xilinx Vivado WebPACK with waveform verification.

Low power 16-bit Verilog ALU implementing Integrated Clock Gating(ICG) and 2-stage pipelining with synthesis and power analysis using open-source ASIC tools.

ASIC synthesis and power optimisation of a SipHash core on 65 nm with Synopsys Design Compiler and PrimeTime: baseline, clock gating and multi-VT flows compared on measured PPA, plus a custom PrimeTime TCL reporter that ranks critical paths by cumulative cell power. −78 % dynamic and −52 % leakage against the baseline.

Full VLSI design flow for a 1st-order IIR low-pass filter. It includes VHDL RTL, fixed-point C model, Synopsys DC synthesis with clock gating, and Cadence Innovus place & route. The advanced architecture of the filter applies J-look-ahead, pipelining, and retiming to achieve 581 MHz, a 47% throughput gain over the standard architecture.