Build software better, together

olofk / edalize

An abstraction library for interfacing EDA tools

Updated Aug 12, 2026
Python

mshr-h / vscode-verilog-hdl-support

Verilog/SystemVerilog support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Sep 2, 2026
TypeScript

tymonx / logic

Star

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

Updated Nov 25, 2019
SystemVerilog

suoto / hdl_checker

Star

Repurposing existing HDL tools to help writing better code

Updated Jun 21, 2026
Python

loykylewong / FPGA-Application-Development-and-Simulation

Star

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Updated Aug 18, 2026
Scala

Paebbels / JSON-for-VHDL

Star

A JSON library implemented in VHDL.

parser json fpga simulation vhdl xilinx synthesis lattice fileformat modelsim questasim ghdl

Updated Jul 13, 2026
VHDL

prajwalgekkouga / AHB-to-APB-Bridge

Star

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

fpga digital verilog modelsim amba apb ahb verilog-project

Updated Oct 7, 2022
Verilog

MJoergen / HyperRAM

Star

Portable HyperRAM controller

fpga vhdl intel xilinx vivado altera lattice modelsim questasim avalon quartus artix questa hyperram

Updated Dec 8, 2024
VHDL

25th-engineer / HFUT_2020_MIPS_CPU

Star

合肥工业大学2020年《系统硬件综合设计》（《计算机组成原理》课程设计，CPU）的代码与报告；使用Verilog实现全冒险处理机制的MIPS五段流水CPU，支持MIPS-C3的50条指令。

cpu verilog vivado modelsim mips-c3

Updated Sep 25, 2020
Assembly

RomeoMe5 / DDLM

Star

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Updated Sep 15, 2023
Verilog

suoto / vim-hdl

Star

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

productivity vhdl vim-plugins verilog xilinx syntastic syntax-checker altera systemverilog modelsim

Updated Jun 1, 2021
Python

kleverhq / wavepeek

Star

🌊 CLI tool for RTL waveform (VCD/FST/FSDB) inspection

waveform rtl vcs modelsim vcd fst icarus verilator cocotb fsdb xcelium

Updated Aug 23, 2026
Rust

DOUDIU / Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm

Star

The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.

fpga vivado modelsim canny

Updated Apr 22, 2024
Verilog

Stokpan / E80

Star

Educational VHDL computer with a single-click toolchain for assembly, simulation, and execution on FPGAs

cpu max7219 assembly vhdl isa microworld modelsim ghdl yosys quartus gowin gatemate tang-primer-25k

Updated Aug 17, 2026
VHDL

ItzzInfinity / 100-days-of-RTL

Star

Trying to get a new skill

digital electronics rtl verilog xilinx vivado altera modelsim testbench xilinx-vivado quartus-prime gowin

Updated Dec 31, 2024
Verilog

arthurmteodoro / install-quartus-linux

Star

Tutorial de instalação do Quartus Prime no Linux

fpga install-script modelsim quartus-prime quartus-linux fpga-linux

Updated Oct 16, 2019
Shell

erfnzdeh / verilog-fpga-parking-management-system

Star

Synthesisable Verilog controller for a 700-space university car park: independent occupancy and availability tracking for university and visitor vehicles against one shared capacity, with a transcript-generating testbench and an Intel Quartus project.

fpga rtl verilog icarus-verilog hdl modelsim testbench digital-design quartus sharif sharif-university intel-fpga hardware-design

Updated Aug 12, 2026
Verilog

SACHINUR17 / VLSI-Design-Verification-Projects

Star

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

Updated May 23, 2026
SystemVerilog

tianrenz2 / Single-Cycle-Processor

Star

Single-Cycle RISC-V Processor in systemverylog

verification systemverilog modelsim

Updated Apr 23, 2019
SystemVerilog

MUDAL / Altera_FPGA_Projects

Star

Custom Altera FPGA designs by Olaoluwa Raji. This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA using VHDL.

fpga electronics vhdl stm32 embedded-systems modelsim quartus-prime altera-fpga rtl-design-and-verification

Updated Jun 22, 2026
VHDL

Navigation Menu

modelsim

Here are 369 public repositories matching this topic...

olofk / edalize

mshr-h / vscode-verilog-hdl-support

tymonx / logic

suoto / hdl_checker

loykylewong / FPGA-Application-Development-and-Simulation

Paebbels / JSON-for-VHDL

prajwalgekkouga / AHB-to-APB-Bridge

MJoergen / HyperRAM

25th-engineer / HFUT_2020_MIPS_CPU

RomeoMe5 / DDLM

suoto / vim-hdl

kleverhq / wavepeek

DOUDIU / Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm

Stokpan / E80

ItzzInfinity / 100-days-of-RTL

arthurmteodoro / install-quartus-linux

erfnzdeh / verilog-fpga-parking-management-system

SACHINUR17 / VLSI-Design-Verification-Projects

tianrenz2 / Single-Cycle-Processor

MUDAL / Altera_FPGA_Projects

Add this topic to your repo