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netlists

Here are 11 public repositories matching this topic...

VLSIDA / OpenRAM

An open-source static random access memory (SRAM) compiler.

python magic sram gds netgen ngspice netlists

Updated Aug 16, 2026
Python

spydrnet

byuccl / spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

fpga digital hardware transformations eda circuits cad circuit hardware-designs transformation circuit-analysis netlist computer-aided-design fpgas netlist-parser circuit-design electronic-design-automation netlists edif

Updated Apr 27, 2026
Python

f18m / netlist-viewer

SPICE netlist visualizer

electronics circuits spice electrical-engineering netlists circuits-and-electronics

Updated Jul 31, 2026
C++

arasgungore / netlist-solver

A MATLAB project that uses modified nodal analysis to calculate the node voltages of any analog circuit.

Updated Aug 8, 2022
MATLAB

byuccl / spydrnet-tmr

TMR utilities for the SpyDrNet project

fpga digital transformations verilog hardware-designs transformation netlist computer-aided-design fpgas electronic-design-automation tmr triple-modular-redundancy blif netlists edif spydrnet eblif

Updated Nov 7, 2023
Python

FPGAsm / FPGAsm

A low-level hierarchical netlist assembler for FPGAs

fpga netlist netlists hdls

Updated Jul 26, 2021
C++

jvestman / skimibowi

SKiDL Microcontroller Board Wizard

pyqt5 wizard kicad netlist microcontroller-boards netlists circuits-and-electronics

Updated Sep 23, 2023
Python

esch3r / SPICElabs

This repository will include projects and solutions to problems solved and verified with Spice.

circuit-simulator neurons circuit-analysis spice-simulation netlists

Updated Jul 18, 2019
AGS Script

paranlee / guarded_unsigned_counter

Counter with two guardians who count each bit either even or odd.

counter fpga bit rtl verilog icarus-verilog iverilog netlists

Updated Sep 1, 2021
Verilog

amigatronic / eda2eagle

Schematic generator from netlist

Updated Aug 30, 2026
Python

kostasnikolos / -CAD_Projects_Reading-Creating_Components

CAD Tools — (Course: CAD Tools, Semester 8): lab exercises written in C creating a tool for SPICE simulation and architecture output with step-by-step reports and project files.

c spice netlists librariees

Updated Sep 1, 2025
C

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