LLM 文档智能抽取工具 LLM-based document extraction with model fallback, JSON repair state machine, and token cost tracking
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Jun 1, 2026 - Python
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A high-performance 5-stage pipelined RISC-V RV32I core implemented in SystemVerilog with full ISA compliance, hazard detection, and comprehensive verification.
open-source cpu fpga hardware processor verification embedded-systems microprocessor educational systemverilog computer-architecture hazard-detection risc hdl vlsi risc-v digital-design rv32i pipeli pipelined-processor
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Jun 28, 2026 - SystemVerilog
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Nov 10, 2025 - Python
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