A small SoC with a pipeline 32-bit RISC-V CPU.

同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植

Matrix multiplication on multiple Nios II cores

Project for FPGA, VHDL and SoPC course at hepia

Nios II processor based Qsys using Altera Quartus II 18.1 using Cyclone IV FPGA EP4CE10E22C8

Altera Cyclone IV USB stick uses EP4CE22F17C7

Bộ lab FPGA/SoPC HCMUS: Quartus/Platform Designer, Verilog Avalon-MM IP, Nios II C, PIO, timer, DMA, HEX LED và ghi chú Typst.