feat: PowerNetBiasSolver — post-pack vertical bias for power/ground nets#63
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LuSrodri wants to merge 1 commit intotscircuit:mainfrom
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feat: PowerNetBiasSolver — post-pack vertical bias for power/ground nets#63LuSrodri wants to merge 1 commit intotscircuit:mainfrom
LuSrodri wants to merge 1 commit intotscircuit:mainfrom
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…l bias Adds a new PowerNetBiasSolver that runs as the final pipeline step after PartitionPackingSolver. It applies vertical displacement to chips based on their power/ground net connectivity — chips predominantly connected to positive voltage nets (VCC, VDD, V+) are displaced upward, chips predominantly connected to ground nets (GND, VSS) are displaced downward. After biasing, an iterative overlap-resolution pass ensures no chips overlap with the required chipGap. Also extracts the LayoutPipelineSolver06 problem data into a separate .problem.ts file (no UI imports), fixing the IdentifyDecouplingCapsSolver06 test that was failing due to a transitive import of circuit-to-svg. Changes: - lib/solvers/PowerNetBiasSolver/PowerNetBiasSolver.ts (new) - lib/solvers/LayoutPipelineSolver/LayoutPipelineSolver.ts (add pipeline step) - pages/LayoutPipelineSolver/LayoutPipelineSolver06.problem.ts (new) - pages/LayoutPipelineSolver/LayoutPipelineSolver06.page.tsx (slim down) - tests/PowerNetBiasSolver/PowerNetBiasSolver01.test.ts (new, 4 tests) - tests/IdentifyDecouplingCapsSolver/IdentifyDecouplingCapsSolver06.test.ts (fix import)
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Summary
Resolves #12 — bad schematic layout where power and ground chips were placed without any vertical bias, producing tangled, hard-to-read schematics.
Approach: Post-pack
PowerNetBiasSolverphaseThis PR adds a new
PowerNetBiasSolverthat runs as the final step in theLayoutPipelineSolverpipeline, afterPartitionPackingSolverhas placed all partitions.Why post-pack (not in-pack)?
The
PackSolver2minimizes pad-to-pad distance for connected networks. Because power/ground nets span many chips simultaneously, injecting directional bias during packing creates conflicting forces. A clean post-pack pass lets the packing algorithm do its job, then applies deterministic, net-type-aware vertical displacement.Algorithm
isPositiveVoltageSourcenets vsisGroundnets.powerRatio ≥ 0.20andpowerRatio > groundRatioare displaced upward (positive Y in schematic math coordinates). Chips withgroundRatio ≥ 0.20andgroundRatio > powerRatioare displaced downward. Mixed chips (decoupling caps, signal chips) are unaffected.chipGap × 5 × netRatio— scales with how "power-dominant" the chip is.Result
Changes
lib/solvers/PowerNetBiasSolver/PowerNetBiasSolver.ts— new solverlib/solvers/LayoutPipelineSolver/LayoutPipelineSolver.ts— addspowerNetBiasSolveras pipeline step 5;getOutputLayout()prefers bias-corrected layout;visualize()shows final biased statepages/LayoutPipelineSolver/LayoutPipelineSolver06.problem.ts— extracted problem data with no UI imports (fixes transitivecircuit-to-svgimport error in tests)pages/LayoutPipelineSolver/LayoutPipelineSolver06.page.tsx— simplified to import from.problem.tstests/PowerNetBiasSolver/PowerNetBiasSolver01.test.ts— 4 tests: direct solver with flat layout, overlap resolution, full pipeline ordering, ExampleCircuit02 regressionTest results
/claim #12