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Preserve legal through-via connectivity in coincident gap-fill regions - #171
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Validation: repro assertion fails on unchanged upstream and passes with the fix. All 115 tests, typecheck, formatting, and build pass. A 96-case audit (48 fixtures, one and four gap-fill passes) preserves exact per-layer geometry and copper/target metadata. The real sample24 topology also retains the repaired eight-layer via region. Same-machine SRJ18 comparison on autorouter
Not performance-neutral: sample6 rises from 2366 to 3072 MiB and 104.0 to 113.0 s. An independent fixed-then-baseline repeat confirms 3064 vs 2384 MiB and 112.6 vs 103.6 s. Both outputs pass DRC; both keep the same 2M native iteration limit. Route choices change, and sample6's joint DRC-repair phase takes longer (25.9 vs 7.5 s), but phase timings alone do not prove where RSS peaks. Leaving this draft because of that reproducible memory regression. No DRC rules, search budgets, or downstream solver logic were changed. This fixes the missing gap-fill via region, not the complete sample24 solve. |
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/benchmark --dataset 18 --same-machine |
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/benchmark --same-machine --dataset 18 |
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/benchmark --same-machine --dataset 24 |
Gap filling splits the same empty XY region into separate nodes on every layer, hiding a legal through-via location beside MP1.4 in SRJ24 sample024. Coalesce identical final-pass gap rectangles only when they cover every board layer, contain no copper or targets, and fit the physical via pad plus its required clearance. Existing obstacle padding is credited once; per-layer free-space coverage and copper ownership are preserved.
Stacked on repro #172. Both the cropped repro and sample024’s actual global mesh restore one eight-layer region at MP1.4, with unchanged 5.6564 × 0.9068 mm dimensions and room for the complete 0.60 mm pad/clearance envelope. This is one isolated contributor to routing sample 24.
Validation: source CI has 119 passed, one skipped, zero failures; ESM/DTS build passes. A geometry audit preserves free-space union and copper metadata across 96 fixture/pass combinations. Consumer CI has 899 passed, 65 skipped, zero failures across all nine shards, with build/type checks passing. Relevant SVGs were inspected.
Draft — performance regression remains. The full paired SRJ18 run is 16/16 DRC clean on both revisions; median time improves 5.5% and memory P90 improves 9.6%. However, an isolated paired sample2 run confirms a runtime increase from 89.4s to 105.3s (+17.8%), with 42 fewer vias and lower peak RSS. Its high-density routing work increases. The previous sample6/14 outliers now produce identical final routing SVGs and work counts to baseline. Full paired SRJ24 validation is complete: completion stays 19/26, DRC-clean outcomes stay 17/26, the same 12 DRC issues remain, and both revisions have six timeouts. DRC error types/messages are unchanged on every board. Median time improves 3.0%; memory P50 is +0.6%, P80 -8.0%, and P90 +2.5%. The full dataset runs show no routing/DRC outcome regressions.
Integration, exact benchmark reports, and remaining acceptance work: tscircuit/tscircuit-autorouter#3234. Do not call this regression-free or ready to merge while the sample2 runtime cost remains.