Repository navigation

RISCV-CPU

Public

About

A FPGA-supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL. Achieve good performance due to optimizations like branch prediction and cache.

9 stars

1 watching

Report repository

Name		Name	Last commit message	Last commit date
Bitstream		Bitstream
Submit FPGA version		Submit FPGA version
Testdata		Testdata
.gitignore		.gitignore
Basys-3-Master.xdc		Basys-3-Master.xdc
README.md		README.md
block_ram.v		block_ram.v
cache.v		cache.v
cpu.v		cpu.v
dcache.v		dcache.v
defines.v		defines.v
document.md		document.md
ex.v		ex.v
ex_mem.v		ex_mem.v
fifo.v		fifo.v
hci.v		hci.v
id.v		id.v
id_ex.v		id_ex.v
if.v		if.v
if_id.v		if_id.v
mem.v		mem.v
mem_control.v		mem_control.v
mem_wb.v		mem_wb.v
pc_reg.v		pc_reg.v
pred.v		pred.v
ram.v		ram.v
regfile.v		regfile.v
riscv_top.v		riscv_top.v
stall_control.v		stall_control.v
testbench.v		testbench.v
uart.v		uart.v
uart_baud_clk.v		uart_baud_clk.v
uart_rx.v		uart_rx.v
uart_tx.v		uart_tx.v

Repository files navigation

RISCV-CPU

A RISCV CPU with 5-stage pipeline.

Test performance (Icahe Version on FPGA)

Name	Passed
array_test1	P
array_test2	P
basicopt1	P
bulgarian	P*
expr	P
gcd	P
hanoi	P*
lvalue2	P
magic	P*
manyarguments	P
multiarray	P
pi	P
qsort	P*
queens	P
statement_test	P*
superloop	P
tak	P

Test performance (Dcahe Version on FPGA)

Name	Passed
array_test1	F
array_test2	F
basicopt1	U
bulgarian	U
expr	U
gcd	U
hanoi	F
lvalue2	U
magic	P
manyarguments	F
multiarray	F
pi	P
qsort	F
queens	U
statement_test	F
superloop	F
tak	F

Test performance (Pred Version not on FPGA)

Name	Passed
array_test1	U
array_test2	U
basicopt1	P
bulgarian	P
expr	P
gcd	P
hanoi	U
lvalue2	U
magic	P
manyarguments	U
multiarray	U
pi	U
qsort	P
queens	P
statement_test	U
superloop	U
tak	U

About

A FPGA-supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL. Achieve good performance due to optimizations like branch prediction and cache.

9 stars

1 watching

Report repository

Releases

Packages

Contributors

Languages