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SPTM Hypervisor - #8
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Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
Program the guarded guest event-stream state through CNTKCTL_EL12 and rescale XNU's 24 MHz event index to the architectural counter frequency. Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
Rearm the physical EL2 timer after guest deadline changes, time-offset updates, and host tick programming so the emulated Apple deadline is serviced on time. Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
Stage live PTE changes before publication and split existing block mappings with break-before-make. Prepare child tables before installing their parent descriptors, and keep asynchronous handlers out of identity-map breaks. Co-Authored-By: Niklas Sheth <hi@niklassheth.com> Signed-off-by: Cody Ho <codyho@stanford.edu>
Add mmu_retype_mapping() to invalidate an existing mapping and publish the break before installing its replacement attributes and permissions. Use the live page-table publication machinery for both phases. Co-Authored-By: Niklas Sheth <hi@niklassheth.com> Signed-off-by: Cody Ho <codyho@stanford.edu>
Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
Convert all ordinary aliases of selected RAM pages between Normal-WB and Normal-NC with cache maintenance and break-before-make. Provide an optional dedicated NC alias for live IOMMU tables, and validate mapping state before transitions. Co-Authored-By: Niklas Sheth <hi@niklassheth.com> Signed-off-by: Cody Ho <codyho@stanford.edu>
Clean framebuffer data before changing cache attributes, then invalidate all four ordinary aliases before installing Normal-NC mappings. Co-Authored-By: Niklas Sheth <hi@niklassheth.com> Signed-off-by: Cody Ho <codyho@stanford.edu>
Remove the iBoot handoff lookup and special uncached mappings from MMU initialization, including the early /vram conversion. Default RAM mappings no longer carve out the handoff region; framebuffer mapping remains in the framebuffer and display setup paths. Co-Authored-By: Niklas Sheth <hi@niklassheth.com> Signed-off-by: Cody Ho <codyho@stanford.edu>
Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
Use the ADT-derived CPU/CPM power-register guard on T8132, T8140, T6040 and T6041. EL2 retains control of the live power registers while the guest reads back its writes from a width-aware shadow. Reads of registers without a shadow continue to use the underlying hardware. Replace the separate T8140 guard with this implementation and keep it in hv_power_register_guard.c. Install its hooks after the guest device mappings are established. Co-Authored-By: Niklas Sheth <hi@niklassheth.com> Signed-off-by: Cody Ho <codyho@stanford.edu>
Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
niklassheth
reviewed
Oct 15, 2026
| case 49: /* REG_SNAPSHOT */ | ||
| ctx->regs[0] = SPTM_STATUS_SUCCESS; | ||
| return true; | ||
| case 12: /* CONFIGURE_ROOT */ |
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Reading through my code again with more knowledge (and better models), I see a lot of room for improvement. There's a lot of duplicate code like this, I’ll send a PR to clean up the emulator
| self.log("Guest is shutting down CPU") | ||
| self.p.hv_exit_cpu() | ||
| del self.started_cpus[self.ctx.cpu_id] | ||
| elif enc in self.sysreg_ro_overrides: |
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I haven't hit either of these logs, are you hitting this path? If so, this might be neo specific
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very possibly, this is definitely required to boot on my neo-- this device appears particularly cursed, i'll do some A/B testing of the neo vs the m4 max
Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
Track writable XNU commpage frames through SPTM retyping and publish the fallback policy when the first shared region is nested. This replaces Python patches that depend on fixed physical addresses. Keep the existing timebase, continuous-clock and TPRO fallbacks. On the recognized 64-bit commpage, clear only CPU capability bits 28 and 29 in both the 64-bit word and its 32-bit mirror. Either bit selects the unsupported AMX path in the tested macOS vDSP dispatcher; all other capabilities are preserved. Check the commpage signature before accessing these fields because other writable commpage frames have a different layout. This avoids locating or modifying XNU AMX globals. The commpage-only policy was verified on Neo with About This Mac, large vDSP operations, and single- and double-precision matrix multiplication. Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
Configure SMCR_EL2 for SME guests so primary and secondary CPUs expose the maximum streaming vector length, including ZT0 access. Keep this independent of the SPTM commpage fallback policy. Assisted-By: OpenAI Codex (GPT-5.6 Sol) Signed-off-by: Niklas Sheth <hi@niklassheth.com>
Pass amfi_allow_only_tc_override=2 in the default M4-class guest boot arguments required by macOS 26.6.2. Assisted-By: LLM Signed-off-by: Cody Ho <codyho@stanford.edu>
The AMCC RORGN registers retain the host firmware physical range when XNU is relocated in guest memory, causing validation of its kernel image to fail. Derive the guest range from its Mach-O segments and override trapped reads. Assisted-By: LLM Signed-off-by: Cody Ho <codyho@stanford.edu>
Pass reads of S3_1_C15_C13_3 through to hardware locally. A boot profile recorded 6,329 Python callbacks and 10.15 seconds of handler time in 22 seconds; local handling avoids those callbacks and their protocol requests. Handle per-CPU CLPC HVCs without the global hypervisor lock, retaining HVC return-PC semantics and locking for shared SPTM services. Assisted-By: LLM Signed-off-by: Jan Marek <janmarek98@proton.me>
Size the boot reservation and page-table bookkeeping from managed RAM and mapped ranges. Include per-page metadata and table storage so larger memory configurations do not exhaust fixed boot limits. Check allocator bounds without overflowing address arithmetic. Assisted-By: LLM Signed-off-by: Jan Marek <janmarek98@proton.me>
Raise the DART record capacity from 32 to 64 to accommodate the instances configured on M4 Pro and Max platforms. Assisted-By: LLM Signed-off-by: Jan Marek <janmarek98@proton.me>
Program the NVMMU count for its 64 hardware tags using the zero-based value 63, independently of the submission queue depth. Assisted-By: LLM Signed-off-by: Jan Marek <janmarek98@proton.me>
Set VMPIDR_EL2 from MPIDR_EL1 on primary and secondary guest entry. Stale firmware values can select another CPU record during XNU startup and leave a secondary CPU spinning before it comes online. Assisted-By: LLM Signed-off-by: Jan Marek <janmarek98@proton.me>
Allocate and initialize TXM channels for every supported CPU slot while retaining the ADT CPU count for the guest CPU map. T6041 XNU consumes sixteen channels even when the ADT contains fewer CPU IDs. Assisted-By: LLM Signed-off-by: Jan Marek <janmarek98@proton.me>
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This PR adds support for the SPTM enabled hypervisor for the base M4 and MacBook Neo on firmware 26.6.2.
The majority of the code, including all of the SPTM emulator, was written by Niklas and carries his signed off by. In areas where I made modifications, his co-authorship is preserved.
It does NOT work on the M4 Max. I have a private branch where it does work, but I do not want to push this due to copyright reasons. See the attached document on the changes required to enable M4 Max (and presumably M4 Pro).
Tested on MacBook Neo.
Changes made to Niklas's patchset:
M4 Max Bringup Requirements: