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Use Tcl_Size for all tcl functions returning sizes. #323

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hzeller wants to merge 2 commits into from
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Use Tcl_Size for all tcl functions returning sizes. #323

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f66cc56
Use `Tcl_Size` for all tcl functions returning sizes.
hzeller Mar 28, 2026
66ee2e2
Use non-deprecated trace add variable syntax.
hzeller Mar 28, 2026
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48 changes: 24 additions & 24 deletions tcl/StaTclTypes.i
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Original file line number Diff line number Diff line change
Expand Up @@ -415,7 +415,7 @@ using namespace sta;
}

%typemap(in) Transition* {
int length;
Tcl_Size length;
const char *arg = Tcl_GetStringFromObj($input, &length);
Transition *tr = Transition::find(std::string_view(arg, length));
if (tr == nullptr) {
Expand All @@ -433,7 +433,7 @@ using namespace sta;
}

%typemap(in) RiseFall* {
int length;
Tcl_Size length;
const char *arg = Tcl_GetStringFromObj($input, &length);
const RiseFall *rf = RiseFall::find(std::string_view(arg, length));
if (rf == nullptr) {
Expand All @@ -451,7 +451,7 @@ using namespace sta;
}

%typemap(in) RiseFallBoth* {
int length;
Tcl_Size length;
const char *arg = Tcl_GetStringFromObj($input, &length);
const RiseFallBoth *rf = RiseFallBoth::find(std::string_view(arg, length));
if (rf == nullptr) {
Expand All @@ -469,7 +469,7 @@ using namespace sta;
}

%typemap(in) PortDirection* {
int length;
Tcl_Size length;
const char *arg = Tcl_GetStringFromObj($input, &length);
PortDirection *dir = PortDirection::find(arg);
if (dir == nullptr) {
Expand All @@ -481,7 +481,7 @@ using namespace sta;
}

%typemap(in) TimingRole* {
int length;
Tcl_Size length;
const char *arg = Tcl_GetStringFromObj($input, &length);
const TimingRole *role = TimingRole::find(arg);
if (role)
Expand All @@ -498,7 +498,7 @@ using namespace sta;
}

%typemap(in) LogicValue {
int length;
Tcl_Size length;
std::string arg = Tcl_GetStringFromObj($input, &length);
if (arg == "0" || stringEqual(arg, "zero"))
$1 = LogicValue::zero;
Expand All @@ -517,7 +517,7 @@ using namespace sta;
}

%typemap(in) AnalysisType {
int length;
Tcl_Size length;
const char *arg = Tcl_GetStringFromObj($input, &length);
if (stringEqual(arg, "single"))
$1 = AnalysisType::single;
Expand Down Expand Up @@ -831,7 +831,7 @@ using namespace sta;
}

%typemap(in) MinMax* {
int length;
Tcl_Size length;
char *arg = Tcl_GetStringFromObj($input, &length);
// Swig is retarded and drops const on args.
MinMax *min_max = const_cast<MinMax*>(MinMax::find(arg));
Expand All @@ -852,7 +852,7 @@ using namespace sta;
}

%typemap(in) MinMaxAll* {
int length;
Tcl_Size length;
char *arg = Tcl_GetStringFromObj($input, &length);
// Swig is retarded and drops const on args.
MinMaxAll *min_max = const_cast<MinMaxAll*>(MinMaxAll::find(arg));
Expand All @@ -865,7 +865,7 @@ using namespace sta;
}

%typemap(in) MinMaxAllNull* {
int length;
Tcl_Size length;
char *arg = Tcl_GetStringFromObj($input, &length);
if (stringEqual(arg, "NULL"))
$1 = nullptr;
Expand All @@ -887,7 +887,7 @@ using namespace sta;

// SetupHold is typedef'd to MinMax.
%typemap(in) const SetupHold* {
int length;
Tcl_Size length;
char *arg = Tcl_GetStringFromObj($input, &length);
// Swig is retarded and drops const on args.
if (stringEqual(arg, "hold")
Expand All @@ -904,7 +904,7 @@ using namespace sta;

// SetupHoldAll is typedef'd to MinMaxAll.
%typemap(in) const SetupHoldAll* {
int length;
Tcl_Size length;
char *arg = Tcl_GetStringFromObj($input, &length);
// Swig is retarded and drops const on args.
if (stringEqual(arg, "hold")
Expand All @@ -925,7 +925,7 @@ using namespace sta;

// EarlyLate is typedef'd to MinMax.
%typemap(in) const EarlyLate* {
int length;
Tcl_Size length;
char *arg = Tcl_GetStringFromObj($input, &length);
// Swig is retarded and drops const on args.
EarlyLate *early_late = const_cast<EarlyLate*>(EarlyLate::find(arg));
Expand All @@ -939,7 +939,7 @@ using namespace sta;

// EarlyLateAll is typedef'd to MinMaxAll.
%typemap(in) const EarlyLateAll* {
int length;
Tcl_Size length;
char *arg = Tcl_GetStringFromObj($input, &length);
// Swig is retarded and drops const on args.
EarlyLateAll *early_late = const_cast<EarlyLateAll*>(EarlyLateAll::find(arg));
Expand All @@ -952,7 +952,7 @@ using namespace sta;
}

%typemap(in) TimingDerateType {
int length;
Tcl_Size length;
char *arg = Tcl_GetStringFromObj($input, &length);
if (stringEqual(arg, "net_delay"))
$1 = TimingDerateType::net_delay;
Expand All @@ -967,7 +967,7 @@ using namespace sta;
}

%typemap(in) TimingDerateCellType {
int length;
Tcl_Size length;
char *arg = Tcl_GetStringFromObj($input, &length);
if (stringEqual(arg, "cell_delay"))
$1 = TimingDerateCellType::cell_delay;
Expand All @@ -980,7 +980,7 @@ using namespace sta;
}

%typemap(in) PathClkOrData {
int length;
Tcl_Size length;
std::string arg = Tcl_GetStringFromObj($input, &length);
if (stringEqual(arg, "clk"))
$1 = PathClkOrData::clk;
Expand All @@ -993,7 +993,7 @@ using namespace sta;
}

%typemap(in) ReportSortBy {
int length;
Tcl_Size length;
std::string arg = Tcl_GetStringFromObj($input, &length);
if (stringEqual(arg, "group"))
$1 = sort_by_group;
Expand All @@ -1006,7 +1006,7 @@ using namespace sta;
}

%typemap(in) ReportPathFormat {
int length;
Tcl_Size length;
std::string arg = Tcl_GetStringFromObj($input, &length);
if (stringEqual(arg, "full"))
$1 = ReportPathFormat::full;
Expand Down Expand Up @@ -1188,7 +1188,7 @@ using namespace sta;
if (Tcl_ListObjGetElements(interp, $input, &argc, &argv) == TCL_OK
&& argc > 0) {
for (int i = 0; i < argc; i++) {
int length;
Tcl_Size length;
const char *mode_name = Tcl_GetStringFromObj(argv[i], &length);
Mode *mode = sta->findMode(mode_name);
if (mode)
Expand All @@ -1215,7 +1215,7 @@ using namespace sta;

%typemap(in) Scene* {
sta::Sta *sta = Sta::sta();
int length;
Tcl_Size length;
std::string scene_name = Tcl_GetStringFromObj($input, &length);
// parse_scene_or_all support depreated 11/21/2025
if (scene_name == "NULL")
Expand Down Expand Up @@ -1248,7 +1248,7 @@ using namespace sta;
if (Tcl_ListObjGetElements(interp, $input, &argc, &argv) == TCL_OK
&& argc > 0) {
for (int i = 0; i < argc; i++) {
int length;
Tcl_Size length;
const char *scene_name = Tcl_GetStringFromObj(argv[i], &length);
Scene *scene = sta->findScene(scene_name);
if (scene)
Expand All @@ -1274,7 +1274,7 @@ using namespace sta;
}

%typemap(in) PropertyValue {
int length;
Tcl_Size length;
const char *arg = Tcl_GetStringFromObj($input, &length);
$1 = PropertyValue(arg);
}
Expand Down Expand Up @@ -1411,7 +1411,7 @@ using namespace sta;
}

%typemap(in) CircuitSim {
int length;
Tcl_Size length;
std::string arg = Tcl_GetStringFromObj($input, &length);
if (stringEqual(arg, "hspice"))
$1 = CircuitSim::hspice;
Expand Down
10 changes: 5 additions & 5 deletions tcl/TclTypeHelpers.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ tclListStringSeq(Tcl_Obj *const source,
StringSeq seq;
if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK) {
for (int i = 0; i < argc; i++) {
int length;
Tcl_Size length;
const char *str = Tcl_GetStringFromObj(argv[i], &length);
seq.push_back(str);
}
Expand All @@ -58,7 +58,7 @@ tclListStringSeqPtr(Tcl_Obj *const source,
if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK) {
StringSeq *seq = new StringSeq;
for (int i = 0; i < argc; i++) {
int length;
Tcl_Size length;
const char *str = Tcl_GetStringFromObj(argv[i], &length);
seq->push_back(str);
}
Expand All @@ -78,7 +78,7 @@ tclListStringSet(Tcl_Obj *const source,
if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK) {
StringSet *set = new StringSet;
for (int i = 0; i < argc; i++) {
int length;
Tcl_Size length;
const char *str = Tcl_GetStringFromObj(argv[i], &length);
set->insert(str);
}
Expand Down Expand Up @@ -183,11 +183,11 @@ arcDcalcArgTcl(Tcl_Obj *obj,
{
Sta *sta = Sta::sta();
sta->ensureGraph();
int list_argc;
Tcl_Size list_argc;
Tcl_Obj **list_argv;
if (Tcl_ListObjGetElements(interp, obj, &list_argc, &list_argv) == TCL_OK) {
const char *input_delay = "0.0";
int length;
Tcl_Size length;
if (list_argc == 6)
input_delay = Tcl_GetStringFromObj(list_argv[5], &length);
if (list_argc == 5 || list_argc == 6) {
Expand Down
30 changes: 15 additions & 15 deletions tcl/Variables.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ namespace eval sta {
# Default digits to print after decimal point for reporting commands.
set ::sta_report_default_digits 2

trace variable ::sta_report_default_digits "rw" \
trace add variable ::sta_report_default_digits {read write} \
sta::trace_report_default_digits

proc trace_report_default_digits { name1 name2 op } {
Expand All @@ -47,15 +47,15 @@ proc trace_report_default_digits { name1 name2 op } {
}
}

trace variable ::sta_crpr_enabled "rw" \
trace add variable ::sta_crpr_enabled {read write} \
sta::trace_crpr_enabled

proc trace_crpr_enabled { name1 name2 op } {
trace_boolean_var $op ::sta_crpr_enabled \
crpr_enabled set_crpr_enabled
}

trace variable ::sta_crpr_mode "rw" \
trace add variable ::sta_crpr_mode {read write} \
sta::trace_crpr_mode

proc trace_crpr_mode { name1 name2 op } {
Expand All @@ -72,87 +72,87 @@ proc trace_crpr_mode { name1 name2 op } {
}
}

trace variable ::sta_cond_default_arcs_enabled "rw" \
trace add variable ::sta_cond_default_arcs_enabled {read write} \
sta::trace_cond_default_arcs_enabled

proc trace_cond_default_arcs_enabled { name1 name2 op } {
trace_boolean_var $op ::sta_cond_default_arcs_enabled \
cond_default_arcs_enabled set_cond_default_arcs_enabled
}

trace variable ::sta_gated_clock_checks_enabled "rw" \
trace add variable ::sta_gated_clock_checks_enabled {read write} \
sta::trace_gated_clk_checks_enabled

proc trace_gated_clk_checks_enabled { name1 name2 op } {
trace_boolean_var $op ::sta_gated_clock_checks_enabled \
gated_clk_checks_enabled set_gated_clk_checks_enabled
}

trace variable ::sta_internal_bidirect_instance_paths_enabled "rw" \
trace add variable ::sta_internal_bidirect_instance_paths_enabled {read write} \
sta::trace_internal_bidirect_instance_paths_enabled

proc trace_internal_bidirect_instance_paths_enabled { name1 name2 op } {
trace_boolean_var $op ::sta_internal_bidirect_instance_paths_enabled \
bidirect_inst_paths_enabled set_bidirect_inst_paths_enabled
}

trace variable ::sta_clock_through_tristate_enabled "rw" \
trace add variable ::sta_clock_through_tristate_enabled {read write} \
sta::trace_clock_through_tristate_enabled

proc trace_clock_through_tristate_enabled { name1 name2 op } {
trace_boolean_var $op ::sta_clock_through_tristate_enabled \
clk_thru_tristate_enabled set_clk_thru_tristate_enabled
}

trace variable ::sta_preset_clear_arcs_enabled "rw" \
trace add variable ::sta_preset_clear_arcs_enabled {read write} \
sta::trace_preset_clr_arcs_enabled

proc trace_preset_clr_arcs_enabled { name1 name2 op } {
trace_boolean_var $op ::sta_preset_clear_arcs_enabled \
preset_clr_arcs_enabled set_preset_clr_arcs_enabled
}

trace variable ::sta_recovery_removal_checks_enabled "rw" \
trace add variable ::sta_recovery_removal_checks_enabled {read write} \
sta::trace_recovery_removal_checks_enabled

proc trace_recovery_removal_checks_enabled { name1 name2 op } {
trace_boolean_var $op ::sta_recovery_removal_checks_enabled \
recovery_removal_checks_enabled set_recovery_removal_checks_enabled
}

trace variable ::sta_dynamic_loop_breaking "rw" \
trace add variable ::sta_dynamic_loop_breaking {read write} \
sta::trace_dynamic_loop_breaking

proc trace_dynamic_loop_breaking { name1 name2 op } {
trace_boolean_var $op ::sta_dynamic_loop_breaking \
dynamic_loop_breaking set_dynamic_loop_breaking
}

trace variable ::sta_input_port_default_clock "rw" \
trace add variable ::sta_input_port_default_clock {read write} \
sta::trace_input_port_default_clock

proc trace_input_port_default_clock { name1 name2 op } {
trace_boolean_var $op ::sta_input_port_default_clock \
use_default_arrival_clock set_use_default_arrival_clock
}

trace variable ::sta_propagate_all_clocks "rw" \
trace add variable ::sta_propagate_all_clocks {read write} \
sta::trace_propagate_all_clocks

proc trace_propagate_all_clocks { name1 name2 op } {
trace_boolean_var $op ::sta_propagate_all_clocks \
propagate_all_clocks set_propagate_all_clocks
}

trace variable ::sta_propagate_gated_clock_enable "rw" \
trace add variable ::sta_propagate_gated_clock_enable {read write} \
sta::trace_propagate_gated_clock_enable

proc trace_propagate_gated_clock_enable { name1 name2 op } {
trace_boolean_var $op ::sta_propagate_gated_clock_enable \
propagate_gated_clock_enable set_propagate_gated_clock_enable
}

trace variable ::sta_pocv_mode "rw" \
trace add variable ::sta_pocv_mode {read write} \
sta::trace_pocv_mode

proc trace_pocv_mode { name1 name2 op } {
Expand All @@ -171,7 +171,7 @@ proc trace_pocv_mode { name1 name2 op } {
}
}

trace variable ::sta_pocv_quantile "rw" \
trace add variable ::sta_pocv_quantile {read write} \
sta::trace_pocv_quantile

proc trace_pocv_quantile { name1 name2 op } {
Expand Down
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