Skip to content

arm/translate: allow MOV.W Rd,SP (Thumb2 T3) on non-MVE M-profile cores #34

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
Chapoly1305 wants to merge 1 commit into
base: master
Choose a base branch
from
Open

arm/translate: allow MOV.W Rd,SP (Thumb2 T3) on non-MVE M-profile cores #34

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 7 additions & 1 deletion arch/arm/translate.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9572,7 +9572,13 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
uint8_t op0 = (insn >> 15) & 0x1;
uint8_t op1 = (insn >> 12) & 0x3;

if(op0 == 0 && rm != 0xd && rm != 0xf) {
// The rm==0xd (SP) encodings in this space are the ARMv8.1-M MVE
// long-shift instructions (ASRL/LSLL/...), so they are only
// reserved on cores that implement MVE. On a non-MVE M-profile
// core (e.g. Cortex-M33) `MOV.W Rd, SP` (rn==0xf, rm==0xd) is a
// legal plain MOV; without allowing it here the decoder rejects
// it as UNDEFINSTR and real firmware faults/reset-loops.
if(op0 == 0 && rm != 0xf && (rm != 0xd || !ENABLE_ARCH_MVE)) {
tmp = load_reg(s, rn);
tmp2 = load_reg(s, rm);
gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
Expand Down