arm/translate: allow MOV.W Rd,SP (Thumb2 T3) on non-MVE M-profile cores - #34
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arm/translate: allow MOV.W Rd,SP (Thumb2 T3) on non-MVE M-profile cores#34Chapoly1305 wants to merge 1 commit into
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The data-processing shifted-register wide-shift space (op==2) excluded rm==0xd (SP) because those encodings are the ARMv8.1-M MVE long-shift instructions (ASRL/LSLL/...). But MVE only exists on cores that implement it (e.g. Cortex-M55/ M85), not Cortex-M33. On a non-MVE M-profile core, 'MOV.W Rd, SP' (rn==0xf, rm==0xd) is a legal plain MOV; rejecting it as UNDEFINSTR makes real firmware fault. Observed on real EFR32MG21 (Cortex-M33) firmware: a single such encoding caused an endless fault->SYSRESETREQ reset loop, preventing radio bring-up. Gate the rm==0xd exclusion on ENABLE_ARCH_MVE so non-MVE cores decode it as MOV.
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Pull request overview
This PR fixes Thumb-2 decoding for M-profile cores without MVE by allowing rm==SP (0xd) in the wide-shift/data-processing shifted-register space, so MOV.W Rd, SP (Thumb2 T3) is treated as a valid MOV instead of being rejected as an undefined instruction.
Changes:
- Gate the
rm==0xdexclusion onENABLE_ARCH_MVEso only MVE-capable cores reserve those encodings for MVE long-shift instructions. - Add an in-code comment explaining the architectural rationale and the observed real-world failure mode.
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The data-processing shifted-register wide-shift space in the Thumb2
decoder excluded
rm==0xd(SP) unconditionally because those encodingsare ARMv8.1-M MVE long-shift instructions (ASRL/LSLL/...).
But MVE only exists on cores that implement it (Cortex-M55/M85), not
Cortex-M33. On a non-MVE M-profile core,
MOV.W Rd, SP(rn==0xf,rm==0xd) is a legal plain MOV; rejecting it as UNDEFINSTR causes realfirmware to fault.
Observed on real EFR32MG21 (Cortex-M33) Zigbee firmware: a single such
encoding caused an endless fault→SYSRESETREQ reset loop, preventing radio
bring-up.
Fix: Gate the
rm==0xdexclusion onENABLE_ARCH_MVEso non-MVEcores decode it as MOV (
+1 / -1line change).