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Signed-off-by: Arthur Koucher <arthurkoucher@precisioninno.com>
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
…-command-names test: call commands by their full names, brace bus subscripts
The verilog writer now escapes an identifier that cannot be written bare,
so the wb_writer_*digit* netlists round-trip. Their XFAIL entries went
XPASS and the suite reported each one, as it is built to.
Removed, all nine netlists:
CONFORMANCE_EXPECTED_FAIL five xfail() blocks, every netlist in them
now passes: the reader no longer hits
"syntax error, unexpected CONSTVAL_TK"
where a digit-leading name was emitted bare
STRUCTURAL_EXPECTED_FAIL 33 netlists across flat/hier round_trip,
namespace and top_ports; the other cases in
those blocks still fail and stay
top_ports going green is second order. The port list was never reordered
-- it only read that way because the unescaped names were misparsed on
read back.
Entries were matched to the XPASS reports by netlist, path and check, not
by name, so s2_collisions_nc_two_digit.v and
wb_sta_reader_const_upper_x_digit.v stay: both still fail.
//src/... is green: 4389 pass, 4 skipped.
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
Signed-off-by: Arthur Koucher <arthurkoucher@precisioninno.com>
Signed-off-by: Arthur Koucher <arthurkoucher@precisioninno.com>
We can't assume bash to be located in /bin/bash. Only valid way to refer to bash is via /usr/bin/env Signed-off-by: Henner Zeller <h.zeller@acm.org>
Signed-off-by: Arthur Koucher <arthurkoucher@precisioninno.com>
Signed-off-by: Arthur Koucher <arthurkoucher@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
…_sta_0918 Update STA 09/18 main theme is read verilog attributes now through Properties
Signed-off-by: Arthur Koucher <arthurkoucher@precisioninno.com>
The "Loading shapes…" overlay was shown once the initial tech/bounds/heatmaps requests all resolved (if bounds reported shapes not ready) and hidden only by the server's "refresh" push. When that push arrived before the slowest of the initial requests, it hid an overlay that was not yet shown, and the overlay then stayed up forever. While the overlay is shown, also poll bounds and hide it once shapes_ready. Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
grt: maintain used grids incrementally
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
…e_delay_buf_list_drv_res Cts create delay buf list drv res
…date_0924 Bump STA pointer to latest 09/24
nix: prefetch fmtlib for slang
…ld-merge-setup-slack rsz: gate each hold buffer load on its own setup slack
Signed-off-by: Arthur Koucher <arthurkoucher@precisioninno.com>
The smaller neighbor sets change Prim-Dijkstra trees on nets with shared coordinates, which global routing hits on gcell-snapped pins. Placement and resizing results are unchanged; routing differs from there on. - grt: pd1, colocated_pins, overlapping_edges and top_level_term3 logs and route guides. - rsz: repair_fanout7_skip_pin_swap and repair_setup_split_load_hier_only logs (small slack/TNS changes). - ibex_sky130hd and aes_sky130hd metrics and limits, regenerated from bazel runs. ibex DRT::ANT::errors and aes DRT max slew/cap limits keep their previous values so both master and this branch pass. Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
…onotone Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
A virtual clock has no leaf pins and a leaf pin with set_propagated_clock starts no ideal clock network, so neither yields an ideal clock pin. Count only what ClkNetwork::findClkPins would, so a non-propagated virtual clock for I/O constraints no longer forces the clock network rebuild. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Signed-off-by: Henner Zeller <h.zeller@acm.org>
What has been patched locally in #11500 is now available in upstream BCR bazelbuild/bazel-central-registry#10782 It also has been fixed in gawk upstream https://cgit.git.savannah.gnu.org/cgit/gawk.git/commit/?id=5fba4975a3ecd074be40593455f23d8df1772e49 ... but that will take to 5.4.2 until available. So until then, the BCR version patches it. Signed-off-by: Henner Zeller <h.zeller@acm.org>
…_actions/actions-4b2c77c676 build(deps): bump the actions group with 2 updates
This reverts commit bf6b494. Signed-off-by: Arthur Koucher <arthurkoucher@precisioninno.com>
Signed-off-by: Arthur Koucher <arthurkoucher@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
…deal-clocks est: no clock network rebuild to find ideal clocks when there are none
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
Use latest gawk that has environment overwriting fixed.
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
…onotone stt: faster PD nearest neighbors with shared-coordinate handling
…ix_wns_mismatch
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
The elaborator lowers latches (e.g. a latch-based clock gate) to feedback muxes. syn cuts such a loop with a loop_breaker and optimizes it as combinational logic, which does not preserve the state the loop holds. For ibex's prim_clock_gating the enable dropped out entirely, leaving AND2(clk_i, clk) -> clk; CTS then recursed around that loop until the stack overflowed. synthesize now checks for combinational loops after the full bitblast and fails with SYN-0080, naming nets on each loop (SYN-0079). Loops are found as strongly connected components of a per-pin dependency graph: a liberty cell output depends only on the inputs in its function or three_state expression, or with a combinational or tristate timing arc to it. An output with neither, such as a RAM read port, breaks the loop. Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
Unnamed nets on a reported loop print as %<id>, which dump_fanin_cone accepts, instead of being dropped; unnamed loop-breaker aliases are skipped. Vector bit names use the same from/to mapping as resolveNetRef. Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
…loop-check syn: reject combinational loops in synthesize
Cmake Removal Date 11/1
…tor-order-wires odb: more refactoring of tmg_conn
Add some missing dependencies.
…nal-heatmaps web: support external heat maps from CSV
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