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1. Voting_Machine Voting_Machine Public

   Voting machine implemented in verilog

   Verilog 10 2

2. Synchronous_RAM_design Synchronous_RAM_design Public

   Random Access Memories designed in Verilog

   Verilog

3. synchronous_fifo synchronous_fifo Public

   Verilog

4. Parameterized-Designs Parameterized-Designs Public

   Verilog designs that are parameterized to fit any value of parameter.

   Verilog

5. sequence_detector_mealy sequence_detector_mealy Public

   Detect the sequence 11x1 in verilog using mealy FSM.

   Verilog