Add baremetal RISC-V smoke tests (rv32, rv64)#19917
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/19917
Note: Links to docs will display an error until the docs builds have been completed. ❌ 3 New Failures, 5 Pending, 1 Unrelated Failure, 12 Unclassified FailuresAs of commit a32f457 with merge base e88fd04 ( NEW FAILURES - The following jobs have failed:
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This PR needs a
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Cross-compiles with riscv64-unknown-elf + picolibc, embeds the .bpte into
the ELF, and runs under qemu-system-riscv{32,64} -machine virt with
semihosting carrying stdout and exit status. Same bundled-IO PASS criterion
as the existing linux runs.
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@claude Review this PR. |
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Claude finished @rascani's task in 2m 51s —— View job Review: Add baremetal RISC-V smoke tests (rv32, rv64)
Overall this is a well-structured PR that cleanly extends the existing RISC-V linux testing to baremetal (rv32 + rv64) using QEMU system mode with semihosting. The architecture mirrors Bugs1. Stale preset path in The default set(EXECUTORCH_BUILD_PRESET_FILE
"${EXECUTORCH_ROOT}/tools/cmake/preset/riscv64_baremetal.cmake" # ← doesn't existThis won't break CI (because 2. Stale path filter in - tools/cmake/preset/riscv64_*.cmakeThe preset files were renamed to 3. Stale reference to echo "[run.sh] ERROR: ${qemu} not found on PATH; install with examples/riscv/setup.sh" >&2
Minor Issues4. README The table shows only 5. README link to see [setup.sh](setup.sh)This is a broken link since the file was renamed. Design Observations (non-blocking)
SummaryThree bugs that should be fixed before merge (stale file references after the |
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Thanks for putting this together @luhenry! |
sentencepiece fails to compile on GCC 15 due to missing #include <cstdint>
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@luhenry Thanks for putting this together. From the MCU / bare-metal angle we discussed in #19666, this looks like the right RV32/RV64 portable-kernel CI baseline to me. One question: |
Yes, Portable Kernels is the baseline. A following contribution could be to add a rv64gc scalar and a rv64gc+RVV backend so that we can have that as a baseline for future RISC-V contributions.
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I updated
This table explicitely doesn't contain the following combinations:
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compiling |
Unfortunately not, but I'm looking into it. |
Looks they're not available externally, so the best bet is probably to build it locally. I can also give it a shot if you're not able to. |
Bumps the sentencepiece submodule from d8f7418 (Aug 2024) to bcc6390 (Jul 2025, google/sentencepiece#1109). The key change is a missing `#include <cstdint>` in sentencepiece_processor.h that causes build failures under GCC 15 (Ubuntu 26.04), which no longer implicitly includes cstdint through transitive headers. This unblocks pytorch/executorch#19917 (RISC-V baremetal CI) which uses the gcc15 docker image. Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
### Summary Updates extension/llm/tokenizers to include meta-pytorch/tokenizers#193, which bumps the sentencepiece submodule to pick up a missing `#include <cstdint>` (google/sentencepiece#1109). Without this, `pytorch_tokenizers` fails to compile inside the `executorch-ubuntu-26.04-gcc15` docker image, blocking the RISC-V baremetal CI (#19917). ### Test plan CI --------- Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
Summary
This adds testing on CI and with local script of the portable backend on baremetal for RISC-V. It cross-compiles with riscv64-unknown-elf + picolibc, embeds the .bpte into the ELF, and runs under
qemu-system-riscv{32,64}with semihosting. We use the same bundled-IO PASS criterion as the existing linux runs for pass/fail.Test plan
The CI is the testing plan as we add configurations to CI. I've validated it works locally with
examples/riscv/test-matrix.sh.cc @psiddh @AdrianLundell @digantdesai @rascani