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Refactored Check-in - #336

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Refactored Check-in#336
Jackcuii wants to merge 50 commits into
masterfrom
codex/master-register-bank-798aaf5

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Jackcuii and others added 30 commits March 29, 2026 09:05
- Add CgraRTL_relu4x4_test_from_yaml.py: ReLU kernel test on 4x4 Mesh CGRA
  using relu.yaml compiled kernel config (II=5, 32 iterations)
- Fix script_generator.py: swap STORE src_operands to match MemUnitRTL
  hardware expectation (in0=address, in1=data vs YAML order [data, addr])
…flag

Bug #1 - CrossbarRTL all-or-nothing: Stale prologued data blocked entire crossbar
- Mask recv_valid_vector, exclude prologued from send/recv_required_vector
- Gate changed: recv_valid_or_prologue_allowing_vector

Bug #2 - PhiRTL shared first flag: Multiple PHI_START on same tile failed
- Detect iteration wrap via ctrl_addr, clear s.first only at boundaries
- Added prev_ctrl_addr tracking

Tests: ReLU 379 cycles (pass), SpMV 759 cycles (pass)
Jackcuii and others added 19 commits April 15, 2026 07:51
OPT_STR set waddr.val and wdata.val based only on input val signals
without checking predicate. During pipeline drain cycles, data with
predicate=0 but val=1 caused spurious stores that overwrote correct
results (e.g., y[0]=30 overwritten by 0 in GEMV kernel).

Gate waddr.val and wdata.val on both inputs' predicates, consistent
with OPT_STR_CONST which already does this correctly.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
# Conflicts:
#	fu/single/CompRTL.py
#	fu/single/test/CompRTL_test.py
# Conflicts:
#	mem/register_cluster/RegisterBankRTL.py

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revert this file?

Comment thread fu/single/PhiRTL.py
recv_str = ",".join([str(x.msg) for x in s.recv_in])
first_str = ",".join([str(x) for x in s.first])
return f'[recv: {recv_str}] {opt_str} (const_reg: {s.recv_const.msg}) (first: {first_str})] = [out: {out_str}] (s.recv_opt.rdy: {s.recv_opt.rdy}, {OPT_SYMBOL_DICT[s.recv_opt.msg.operation]}, send[0].val: {s.send_out[0].val}) reached_vector_factor: {s.reached_vector_factor}; vector_factor_counter: {s.vector_factor_counter}; ctrl_addr_inport: {s.ctrl_addr_inport}'

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We can have the newline at the end.

Comment thread lib/util/data_struct_attr.py Outdated
kAttrVectorFactorPower = 'vector_factor_power'
kAttrIsLastCtrl = 'is_last_ctrl'
kAttrReadRegTowards = 'read_reg_towards'
kAttrReadRegRetain = 'read_reg_retain'

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Why we still need this?

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3 participants