Design and implementation of an IEEE-754 single-precision Floating-Point ALU using Verilog HDL
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Jun 16, 2026 - Verilog
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32-bit-processor
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Synthesizable 5-stage pipelined RV32I processor in Verilog featuring full hazard handling (forwarding, load-use stalls, branch flushes) and an integrated 64-cycle 4×4 matrix multiplication coprocessor.
python matrix-multiplication verilog computer-architecture icarus-verilog hardware-acceleration instruction-set-architecture rv32i processor-design forwarding-unit custom-assembler pipelined-processor risk-v risc-v-processor 32-bit-processor gtk-wave verilog-2001 hazard-handling
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Sep 21, 2026 - Verilog
Simulating a 32-bit processor using VHDL
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Mar 30, 2025 - VHDL
A 32-bit CPU in MIPS architecture
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Jun 5, 2025
This is a 32 Bit Processor design with 3 address format and indirect addressing for my computer organization and architecture course
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Dec 6, 2024
The algorithm proposes a prototype to design a 32-bit processor. The processor is capable of performing the task which includes fetching the instructions, decoding the instructions to figure out what operation needs to be performed, on what operands it needs to perform and where to store, write, the result obtained.
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Jul 24, 2023 - Verilog
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